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| ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 tinypower tm a/d type 8-bit otp mcu with dac rev. 1.00 1 march 11, 2010 general description these tinypower tm a/d type 8-bit high performance risc architecture microcontrollers are specifically, de - signed for applications that interface directly to analog sig - nals. the devices include an integrated multi-channel analog to digital converter, pulse width modulation and and dac outputs. with their fully integrated spi and i 2 c functions, design - ers are provided with a means of easy communication with external peripheral hardware. the benefits of inte - grated a/d, pwm and dac functions, in addition to low power consumption, high performance, i/o flexibility and low-cost, provides the device with the versatility for a wide range of products in the home appliance and in - dustrial application areas. some of these products could include electronic metering, environmental moni - toring, handheld instruments, electronically controlled tools, motor driving in addition to many others. the unique holtek tinypower technology also gives the devices extremely low current consumption characteris - tics, an extremely important consideration in the present trend for low power battery powered applications. the usual holtek mcu features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applica - tions require a minimum of external components. features cpu features operating voltage: f sys = 32768hz: 2.2v~5.5v f sys = 4mhz: 2.2v~5.5v f sys = 8mhz: 3.0v~5.5v f sys = 12mhz: 4.5v~5.5v up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v idle/sleep mode and wake-up functions to reduce power consumption oscillator types: external 32768hz crystal -- lxt external rc -- erc internal 4/8/12mhz rc -- hirc external high frequency crystal -- hxt internal 32khz rc -- lirc four operational modes: normal, slow, idle, sleep fully integrated internal 4mhz, 8mhz and 12mhz os- cillator requires no external components all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 12-level subroutine nesting bit manipulation instruction peripheral features otp program memory: 2k 14 ~ 32k16 ram data memory: 128 8 ~ 2304 8 bits watchdog timer function up to 50 bidirectional i/o lines 8 channel 12-bit adc up to 4 channel 12-bit pwm software controlled 4-scom lines lcd driver with 1 / 2 bias multiple pin-shared external interrupts up to three 8-bit programmable timer/event counter with overflow interrupt and prescaler up to one 16-bit programmable timer/event counter with overflow interrupt serial interfaces module - sim for spi or i 2 c time-base functions low voltage reset function low voltage detect function pfd/buzzer for audio frequency generation 12-bit audio dac output wide range of available package types technical document application note ha0075e mcu reset and oscillator circuits application note
selection table part no. program memory data memory i/o timer time base hirc (mhz) rtc (lxt) lcd scom a/d d/a pwm stack package 8-bit 16-bit ht56r22 2k 14 1288 22 2 1 4/8/12 4 12-bit 8 12-bit 1 12-bit3 6 16dip/nsop/ssop 20dip/sop/ssop 24skdip/sop/ssop ht56r23 4k 15 2568 42 2 1 1 4/8/12 4 12-bit 8 12-bit 1 12-bit4 12 28skdip/sop/ssop 44qfp ht56r24 8k 16 6408 42 2 1 1 4/8/12 4 12-bit 8 12-bit 1 12-bit4 12 28skdip/sop/ssop 44qfp ht56r25 16k 16 11528 50 3 1 1 4/8/12 4 12-bit 8 12-bit 1 12-bit4 12 28skdip/sop 28ssop(209mil) 44/52qfp HT56R26 32k 16 23048 50 3 1 1 4/8/12 4 12-bit 8 12-bit 1 12-bit4 12 28skdip/sop 28ssop(209ml) 44/52qfp note: 1. the devices are only available in otp versions. 2. for devices that exist in more than one package formats, the table reflects the situation for the larger package. block diagram the following block diagram illustrates the main functional blocks. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 2 march 11, 2010 ! " pin assignment note: bracketed pin names indicate non-default pinout remapping locations. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 3 march 11, 2010 # $ # % $ % & $ & ' $ ' $ ( ) $ ) ( * $ * $ # + $ + # ( ( # * # ) # ' # & # % # # # ( , # % & ' ) * + ( $ ( - & . % % . # # % ( # - + / ( $ ( - & . % % . # # % ( # - + / ' 0 # # # $ # % $ % & $ & ' $ ' $ ( ) $ ) ( * $ * $ # + $ + # # # ( ( ( 1 ( % ( # , # # + # * # ) # ' # & # % # # # % & ' ) * + , # ( ( $ ( - & . % % . # # % ( # - + / ) 0 ' 0 & $ & % 1 % # $ # % $ % & $ & ' $ ' $ ( - ) $ ) ( # * $ * $ # # + $ + # 1 # % % # # # ( ( ( 1 ( # # % ' % & % % % # % ( # , # # + # * # ) # ' # & # % & ' ) * + , # ( # # # % ( $ ( - & . % % . # # % ( # - + / * * % ) 0 ' 0 & $ & % 1 % # $ # % $ % & $ & ' $ ' $ ( - ) $ ) ( # * $ * $ # # + $ + # 1 # / ( 2 3 # & & % % # # ( ( ( 1 ( # # % % + % * % ) % ' % & % % % # % ( # , # # + # * # ) # % & ' ) * + , # ( # # # % # & # ' ' 2 ( 3 & & % % # # ( ( ( 1 ( # # % 1 % & $ & ' 0 ) 0 # % & ' ) * + , # ( # # # % # & # ' # ) # * # + # # , % ( % # % % % & % ' % ) % * % + % % , & ( & # & % & & & '& )& *& +& & ,' (' #' %' &' ' ) 2 # 3 * 2 # 3 + 2 $ # 3 / ) 2 % 3 / ' / & / % 2 ( 3 / # 2 $ ( 3 / ( 2 3 # + $ + # 1 # * $ * $ # # ) $ ) ( # ' $ ' $ ( - & $ & % $ % # $ # ( $ ( & % # ( - * % + ' ) * + / - ( # # % % . # & . % note: bracketed pin names indicate non-default pinout remapping locations. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 4 march 11, 2010 ' 2 ( 3 & & % % # # ( ( ( 1 ( # # % 1 % & $ & ' 0 ) 0 # % & ' ) * + , # ( # # # % # & # ' # ) # * # + # # , % ( % # % % % & % ' % ) % * % + % % , & ( & # & % & & & '& )& *& +& & ,' (' #' %' &' ' ) 2 # 3 * 2 # 3 + 2 $ # 3 / ) 2 % 3 / ' / & / % 2 ( 3 / # 2 $ ( 3 / ( 2 3 # + $ + # 1 # * $ * $ # # ) $ ) ( # ' $ ' $ ( - & $ & % $ % # $ # ( $ ( & % # ( - * % + & ' ) * + / - ( # # % % . # & . % ( $ ( - & . % % . # # % ( # - + / * * % ) 0 ' 0 & $ & % 1 % # $ # % $ % & $ & ' $ ' $ ( - ) $ ) ( # * $ * $ # # + $ + # 1 # / ( 2 3 # & & % % # # ( ( ( 1 ( # # % % + % * % ) % ' % & % % % # % ( # , # # + # * # ) # % & ' ) * + , # ( # # # % # & # ' # % & ' ) * + , # ( # # # % # & # ' # ) # * # + # # , % ( % # % % & ' & ) & * & + & & , ' ' ,) () #) % % & % ' % ) % * % + % % , & ( & # & % & & ' (' #' %' &' ' ' )' *' + + $ + # 1 # * $ * $ # # ) $ ) ( # ' $ ' $ ( - & $ & % $ % # $ # ( $ ( & % # ( - & & ' 2 ( 3 ) 2 # 3 * 2 # 2 + 2 $ # 3 / + / * / ) 2 % 3 / ' / & / % 2 ( 3 / # 2 $ ( 3 / ( 2 3 # * + " ( " # ' ) * + / - ( # # % % . # & . % % % # # ( ( ( 1 ( # # % 1 % & $ & ' 0 ) 0 * % + & ' ) pin description ht56r22 pin name function opt i/t o/t description pa0/an0 pa0 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an0 adcr an a/d channel 0 pa1/an1 pa1 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an1 adcr an a/d channel 1 pa2/an2 pa2 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an2 adcr an a/d channel 2 pa3/pfd/an3 pa3 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd co pinmap st pfd output an3 adcr an a/d channel 3 pa4/int0/an4/vddio pa4 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int0 pinmap st external interrupt 0 input an4 adcr an a/d channel 4 vddio co pwr vddio power input pa5/tc0/sdo1/an5 pa5 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 pinmap st external timer 0 clock input sdo1 co spictl0 cmos spi1 serial data output an5 adcr an a/d channel 5 pa6/int1/sdi1/an6 pa6 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int1 pinmap st external interrupt 1 input sdi1 co spictl0 cmos spi1 serial data input an6 adcr an a/d channel 6 pa7/tc1/sck1/an7 pa7 pawk st cmos general purpose i/o. register enabled wake-up. tc1 pinmap st external timer 1 clock input sck1 co spictl0 st cmos spi1 serial clock input or output an7 adcr an a/d channel 7 pb0/sck0/scl/scom0 pb0 pbpu st cmos general purpose i/o. register enabled pull-up. sck0 co simctl0 st cmos spi1 serial clock input or output scl co simctl0 st i 2 c serial clock input scom0 scomc scom software controlled 1 / 2 bias lcd com ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 5 march 11, 2010 pin name function opt i/t o/t description pb1/scs0 /scom1 pb1 pbpu st cmos general purpose i/o. register enabled pull-up. scs0 co simctl0 st cmos spi0 select control pin scom1 scomc scom software controlled 1 / 2 bias lcd com pb2/pclk/scom2 pb2 pbpu st cmos general purpose i/o. register enabled pull-up. pclk co simctl0 cmos peripheral clock output scom2 scomc scom software controlled 1 / 2 bias lcd com pb3/pint /scom3 pb3 pbpu st cmos general purpose i/o. register enabled pull-up. pint st peripheral interrupt input, falling edge trigger scom3 scomc scom software controlled 1 / 2 bias lcd com pb4/bz pb4 pbpu st cmos general purpose i/o. register enabled pull-up. bz co buzzer output pb5/bz /aud pb5 pbpu st cmos general purpose i/o. register enabled pull-up. bz co buzzer bar output aud co dactrl ao audio output pc0/osc1 pc0 pcpu st cmos general purpose i/o. register enabled pull-up. osc1 co an oscillator pin pc1/osc2 pc1 pcpu st cmos general purpose i/o. register enabled pull-up. osc2 co cmos oscillator pin pc2/xt1 pc2 pcpu st cmos general purpose i/o. register enabled pull-up. xt1 co cmos oscillator pin pc3/xt2 pc3 pcpu st cmos general purpose i/o. register enabled pull-up. xt2 co lxt oscillator pin pc7/res pc7 pcpu st nmos general purpose i/o. register enabled pull-up. res co st reset input pd0/pwm0/sdi0/sda pd0 pdpu st cmos general purpose i/o. register enabled pull-up. pwm0 pinmap cmos pwm0 output sdi0 co simctl0 st spi0 serial data input sda co simctl0 st od i 2 c data input or output pd1/pwm1/sdo0 pd1 pdpu st cmos general purpose i/o. register enabled pull-up. pwm1 pinmap cmos pwm1 output sdo0 co simctl0 cmos spi0 serial data output pd2/pwm2 /scs1 pd2 pdpu st cmos general purpose i/o. register enabled pull-up. pwm2 pinmap cmos pwm2 output scs1 co spictl0 st cmos spi1 chip select pin vdd vdd pwr power supply vss vss pwr ground ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 6 march 11, 2010 note: i/t: input type; o/t: output type opt: optional by configuration option (co) or register option pwr: power; co: configuration option st: schmitt trigger input; cmos: cmos output; an: analog input scom= software controlled lcd com hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator ht56r23/ht56r24 pin name function opt i/t o/t description pa0/an0 pa0 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an0 adcr an a/d channel 0 pa1/an1 pa1 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an1 adcr an a/d channel 1 pa2/an2 pa2 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an2 adcr an a/d channel 2 pa3/pfd/an3 pa3 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd co pinmap st pfd output an3 adcr an a/d channel 3 pa4/int0/an4/vddio pa4 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int0 pinmap st external interrupt 0 input an4 adcr an a/d channel 4 vddio co pwr vddio power input pa5/tc0/sdo1/an5 pa5 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 pinmap st external timer 0 clock input sdo1 co spictl0 cmos spi1 serial data output an5 adcr an a/d channel 5 pa6/int1/sdi1/an6 pa6 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int1 pinmap st external interrupt 1 input sdi1 co spictl0 cmos spi1 serial data input an6 adcr an a/d channel 6 pa7/tc1/sck1/an7 pa7 pawk st cmos general purpose i/o. register enabled wake-up. tc1 pinmap st external timer 1 clock input sck1 co spictl0 st cmos spi1 serial clock input or output an7 adcr an a/d channel 7 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 7 march 11, 2010 pin name function opt i/t o/t description pb0/sck0/scl/scom0 pb0 pbpu st cmos general purpose i/o. register enabled pull-up. sck0 co simctl0 st cmos spi1 serial clock input or output scl co simctl0 st i 2 c serial clock input scom0 scomc scom software controlled 1 / 2 bias lcd com pb1/scs0 /scom1 pb1 pbpu st cmos general purpose i/o. register enabled pull-up. scs0 co simctl0 st cmos spi0 select control pin scom1 scomc scom software controlled 1 / 2 bias lcd com pb2/pclk/scom2 pb2 pbpu st cmos general purpose i/o. register enabled pull-up. pclk co simctl0 cmos peripheral clock output scom2 scomc scom software controlled 1 / 2 bias lcd com pb3/pint /scom3 pb3 pbpu st cmos general purpose i/o. register enabled pull-up. pint st peripheral interrupt input, falling edge trigger scom3 scomc scom software controlled 1 / 2 bias lcd com pb4/bz pb4 pbpu st cmos general purpose i/o. register enabled pull-up. bz co buzzer output pb5/bz pb5 pbpu st cmos general purpose i/o. register enabled pull-up. bz co buzzer bar output pb6/tc2 pb6 pbpu st cmos general purpose i/o. register enabled pull-up. tc2 st external timer 2 clock input pb7 pb7 pbpu st cmos general purpose i/o. register enabled pull-up. pc0/osc1 pc0 pcpu st cmos general purpose i/o. register enabled pull-up. osc1 co an oscillator pin pc1/osc2 pc1 pcpu st cmos general purpose i/o. register enabled pull-up. osc2 co cmos oscillator pin pc2/xt1 pc2 pcpu st cmos general purpose i/o. register enabled pull-up. xt1 co cmos oscillator pin pc3/xt2 pc3 pcpu st cmos general purpose i/o. register enabled pull-up. xt2 co lxt oscillator pin pc4~pc5 pcn pcpu st cmos general purpose i/o. register enabled pull-up. pc6/aud pc6 pcpu st cmos general purpose i/o. register enabled pull-up. aud co dactrl ao audio output pc7/res pc7 pcpu st nmos general purpose i/o. register enabled pull-up. res co st reset input pd0/pwm0/sdi0/sda pd0 pdpu st cmos general purpose i/o. register enabled pull-up. pwm0 pinmap cmos pwm0 output sdi0 co simctl0 st spi0 serial data input sda co simctl0 st od i 2 c data input or output ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 8 march 11, 2010 pin name function opt i/t o/t description pd1/pwm1/sdo0 pd1 pdpu st cmos general purpose i/o. register enabled pull-up. pwm1 pinmap cmos pwm1 output sdo0 co simctl0 cmos spi0 serial data output pd2/pwm2 pd2 pdpu st cmos general purpose i/o. register enabled pull-up. pwm2 pinmap cmos pwm2 output pd3/pwm3 pd3 pdpu st cmos general purpose i/o. register enabled pull-up. pwm3 cmos pwm3 output pd4/pwm0 pd4 pdpu st cmos general purpose i/o. register enabled pull-up. pwm0 pinmap cmos pwm0 output pd5/pwm1 pd5 pdpu st cmos general purpose i/o. register enabled pull-up. pwm1 pinmap cmos pwm1 output pd6/tc1 pd6 pdpu st cmos general purpose i/o. register enabled pull-up. tc1 pinmap st external timer 1 clock input pd7/int1 pd7 pdpu st cmos general purpose i/o. register enabled pull-up. int1 pinmap st external interrupt 1 input pe0/pfd/scs1 pe0 pepu st cmos general purpose i/o. register enabled pull-up. pfd co pinmap cmos pfd output scs1 co spictl0 st cmos spi1 chip select pin pe1/int0 pe1 pepu st cmos general purpose i/o. register enabled pull-up. int0 pinmap st external interrupt 0 input pe2/tc0 pe2 pepu st cmos general purpose i/o. register enabled pull-up. tc0 pinmap st external timer 0 clock input pe3~pe4 pen pepu st cmos general purpose i/o. register enabled pull-up. pe5/pwm2 pe5 pepu st cmos general purpose i/o. register enabled pull-up. pwm2 pinmap cmos pwm2 output pf0~pf3 pfn pfpu st cmos general purpose i/o. register enabled pull-up. pg0~pg1 pgn pgpu st cmos general purpose i/o. register enabled pull-up. vdd vdd pwr power supply vss vss pwr ground note: i/t: input type; o/t: output type opt: optional by configuration option (co) or register option pwr: power; co: configuration option st: schmitt trigger input; cmos: cmos output; an: analog input scom: software controlled lcd com hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 9 march 11, 2010 ht56r25/HT56R26 pin name function opt i/t o/t description pa0/an0 pa0 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an0 adcr an a/d channel 0 pa1/an1 pa1 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an1 adcr an a/d channel 1 pa2/an2 pa2 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. an2 adcr an a/d channel 2 pa3/pfd/an3 pa3 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd co pinmap st pfd output an3 adcr an a/d channel 3 pa4/int0/an4/vddio pa4 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int0 pinmap st external interrupt 0 input an4 adcr an a/d channel 4 vddio co pwr vddio power input pa5/tc0/sdo1/an5 pa5 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 pinmap st external timer 0 clock input sdo1 co spictl0 cmos spi1 serial data output an5 adcr an a/d channel 5 pa6/int1/sdi1/an6 pa6 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int1 pinmap st external interrupt 1 input sdi1 co spictl0 cmos spi1 serial data input an6 adcr an a/d channel 6 pa7/tc1/sck1/an7 pa7 pawk st cmos general purpose i/o. register enabled wake-up. tc1 pinmap st external timer 1 clock input sck1 co spictl0 st cmos spi1 serial clock input or output an7 adcr an a/d channel 7 pb0/sck0/scl/scom0 pb0 pbpu st cmos general purpose i/o. register enabled pull-up. sck0 co simctl0 st cmos spi1 serial clock input or output scl co simctl0 st i 2 c serial clock input scom0 scomc scom software controlled 1 / 2 bias lcd com ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 10 march 11, 2010 pin name function opt i/t o/t description pb1/scs0 /scom1 pb1 pbpu st cmos general purpose i/o. register enabled pull-up. scs0 co simctl0 st cmos spi0 select control pin scom1 scomc scom software controlled 1 / 2 bias lcd com pb2/pclk/scom2 pb2 pbpu st cmos general purpose i/o. register enabled pull-up. pclk co simctl0 cmos peripheral clock output scom2 scomc scom software controlled 1 / 2 bias lcd com pb3/pint /scom3 pb3 pbpu st cmos general purpose i/o. register enabled pull-up. pint st peripheral interrupt input, falling edge trigger scom3 scomc scom software controlled 1 / 2 bias lcd com pb4/bz pb4 pbpu st cmos general purpose i/o. register enabled pull-up. bz co buzzer output pb5/bz pb5 pbpu st cmos general purpose i/o. register enabled pull-up. bz co buzzer bar output pb6/tc2 pb6 pbpu st cmos general purpose i/o. register enabled pull-up. tc2 st external timer 2 clock input pb7/tc3 pb7 pbpu st cmos general purpose i/o. register enabled pull-up. tc3 st external timer 3 clock input pc0/osc1 pc0 pcpu st cmos general purpose i/o. register enabled pull-up. osc1 co an oscillator pin pc1/osc2 pc1 pcpu st cmos general purpose i/o. register enabled pull-up. osc2 co cmos oscillator pin pc2/xt1 pc2 pcpu st cmos general purpose i/o. register enabled pull-up. xt1 co cmos oscillator pin pc3/xt2 pc3 pcpu st cmos general purpose i/o. register enabled pull-up. xt2 co lxt oscillator pin pc4~pc5 pcn pcpu st cmos general purpose i/o. register enabled pull-up. pc6/aud pc6 pcpu st cmos general purpose i/o. register enabled pull-up. aud co dactrl ao audio output pc7/res pc7 pcpu st nmos general purpose i/o. register enabled pull-up. res co st reset input pd0/pwm0/sdi0/sda pd0 pdpu st cmos general purpose i/o. register enabled pull-up. pwm0 pinmap cmos pwm0 output sdi0 co simctl0 st spi0 serial data input sda co simctl0 st od i 2 c data input or output pd1/pwm1/sdo0 pd1 pdpu st cmos general purpose i/o. register enabled pull-up. pwm1 pinmap cmos pwm1 output sdo0 co simctl0 cmos spi0 serial data output ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 11 march 11, 2010 pin name function opt i/t o/t description pd2/pwm2 pd2 pdpu st cmos general purpose i/o. register enabled pull-up. pwm2 pinmap cmos pwm2 output pd3/pwm3 pd3 pdpu st cmos general purpose i/o. register enabled pull-up. pwm3 cmos pwm3 output pd4/pwm0 pd4 pdpu st cmos general purpose i/o. register enabled pull-up. pwm0 pinmap cmos pwm0 output pd5/pwm1 pd5 pdpu st cmos general purpose i/o. register enabled pull-up. pwm1 pinmap cmos pwm1 output pd6/tc1 pd6 pdpu st cmos general purpose i/o. register enabled pull-up. tc1 pinmap st external timer 1 clock input pd7/int1 pd7 pdpu st cmos general purpose i/o. register enabled pull-up. int1 pinmap st external interrupt 1 input pe0/pfd/scs1 pe0 pepu st cmos general purpose i/o. register enabled pull-up. pfd co pinmap cmos pfd output scs1 co spictl0 st cmos spi1 chip select pin pe1/int0 pe1 pepu st cmos general purpose i/o. register enabled pull-up. int0 pinmap st external interrupt 0 input pe2/tc0 pe2 pepu st cmos general purpose i/o. register enabled pull-up. tc0 pinmap st external timer 0 clock input pe3~pe4 pen pepu st cmos general purpose i/o. register enabled pull-up. pe5/pwm2 pe5 pepu st cmos general purpose i/o. register enabled pull-up. pwm2 pinmap cmos pwm2 output pe6~pe7 pen pepu st cmos general purpose i/o. register enabled pull-up. pf0~pf7 pfn pfpu st cmos general purpose i/o. register enabled pull-up. pg0~pg1 pgn pgpu st cmos general purpose i/o. register enabled pull-up. vdd vdd pwr power supply vss vss pwr ground note: i/t: input type; o/t: output type opt: optional by configuration option (co) or register option pwr: power; co: configuration option st: schmitt trigger input; cmos: cmos output; an: analog input scom: software controlled lcd com hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ................................................................80ma i oh total.............................................................. 80ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 12 march 11, 2010 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.0 5.5 v f sys =12mhz 4.5 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =f m =1mhz 170 250 a 5v 380 570 a i dd2 operating current (crystal osc, rc osc) 3v no load, f sys =f m =2mhz 240 360 a 5v 490 730 a i dd3 operating current (crystal osc, rc osc) 3v no load, f sys =f m =4mhz (note 4) 440 660 a 5v 900 1350 a i dd4 operating current (ec mode, filter on) 3v no load, f sys =f m =4mhz 380 570 a 5v 720 1080 a i dd5 operating current (ec mode, filter off) 3v no load, f sys =f m =4mhz 370 550 a 5v 680 1020 a i dd6 operating current (crystal osc, rc osc) 5v no load, f sys =f m =8mhz 1.8 2.7 ma i dd7 operating current (crystal osc, rc osc) 5v no load, f sys =f m =12mhz 2.6 4.0 ma i dd8 operating current (slow mode, f m =4mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =500khz 150 220 a 5v 340 510 a i dd9 operating current (slow mode, f m =4mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =1mhz 180 270 a 5v 400 600 a i dd10 operating current (slow mode, f m =4mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =2mhz 270 400 a 5v 560 840 a i dd11 operating current (slow mode, f m =8mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =1mhz 240 360 a 5v 540 810 a i dd12 operating current (slow mode, f m =8mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =2mhz 320 480 a 5v 680 1020 a i dd13 operating current (slow mode, f m =8mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =4mhz 500 750 a 5v 1000 1500 a i dd14 operating current f sys = lxt or lirc (note 1) 3v no load, wdt off 69 a 5v 10 15 a i stb1 standby current ( sleep) (f sys ,f sub ,f s ,f wdt =off) 3v no load, system halt, wdt off 0.2 1.0 a 5v 0.3 2.0 a i stb2 standby current ( sleep) (f sys ,f wdt =f sub = lxt or lirc 3v no load, system halt, wdt on 24 a 5v 35 a ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 13 march 11, 2010 symbol parameter test conditions min. typ. max. unit v dd conditions i stb3 standby current ( idle) (f sys =on, f sys =f m =4mhz, f wdt =off, f s (note 2)=f sub =lxt or lirc 3v no load, system halt, wdt off, spi or i 2 c on, pclk on, pclk=f sys /8 150 250 a 5v 350 550 a v il1 input low voltage for i/o ports, tc0/1/2/3 and int0/1 0 0.3v dd v v ih1 input high voltage for i/o ports, tc0/1/2/3 and int0/1 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage configuration option: 2.1v 1.98 2.1 2.22 v configuration option: 3.15v 2.98 3.15 3.32 v configuration option: 4.2v 3.98 4.2 4.42 v v lvd low voltage detector voltage configuration option: 2.2v 2.08 2.2 2.32 v configuration option: 3.3v 3.12 3.3 3.50 v configuration option: 4.4v 4.12 4.4 4.70 v i ol1 i/o port sink current 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh1 i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 8 ma r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k i scom scom operating current 5v scomc, isel=0 17.5 25.0 32.5 a scomc, isel=1 35 50 65 a v scom v dd /2 voltage for lcd com 5v no load 0.475 0.500 0.525 v dd note: 1. lxt is in slow start mode (rtcc.4=qosc=1) for the d.c. current measurement. 2. f s is the internal clock for the buzzer, rtc interrupt, time base interrupt and the wdt. 3. both timer/event counters are off. timer filter is disabled for all test conditions. 4. all peripherals are in off condition if not mentioned at i dd ,i stb tests. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 14 march 11, 2010 ta=25 c a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc, rc osc) 2.2v~5.5v 32 4000 khz 3.0v~5.5v 32 8000 khz 4.5v~5.5v 32 12000 khz f 4merc system clock (erc) 5v r=150k , ta=25 c* 2% 4 +2% mhz 5v r=150k , ta=40 c~+85 c 8% 4 +8% mhz 2.7v~ 5.5v r=150k , ta=40 c~+85 c 15% 4 +15% mhz f 4mirc system clock (hirc) 5v ta=25 c 2% 4 +2% mhz 5v ta=40 c~85 c 5% 4 +5% mhz 2.7v~ 5.5v ta=40 c~85 c 10% 4 +10% mhz f lxt system clock lxt 32768 hz f timer timer i/p frequency (tmr0/tmr1) 2.2v~5.5v 0 4000 khz 3.0v~5.5v 0 8000 khz 4.5v~5.5v 0 12000 khz f lirc lirc oscillator 2.2v~5.5v, after trim 28.8 32.0 35.2 khz t res external reset low pulse width 1 s t lvr low voltage reset time 0.1 0.4 0.6 ms t sst1 system start-up timer period power-on 1024 t sys * t sst2 system start-up timer period for xtal or rtc oscillator wake-up from power down mode 1024 t sys * t sst3 system start-up timer period for external rc or external clock wake-up from power down mode 12 t sys t int interrupt pulse width 1 s note: 1. t sys =1/f sys1 or 1/f sys2 2. * for f 4merc , as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 15 march 11, 2010 adc characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions dnl a/c differential non-linearity 5v t ad =0.5s 2 2 lsb inl adc integral non-linearity 5v t ad =0.5s 4 4 lsb i adc additional power consumption if a/d converter is used 3v 0.50 0.75 ma 5v 1.00 1.50 ma t ad a/d clock period 0.5 s t adc a/d conversion time 16 t ad power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 16 march 11, 2010 - - - ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 17 march 11, 2010 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o and a/d control sys - tem with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crys - tal/resonator or rc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. 4 5 6 7 8 / 9 4 : 6 7 # 8 4 5 6 7 ; # 8 / 9 4 : 6 7 8 4 5 6 7 ; % 8 / 9 4 : 6 7 ; # 8 ; # ; % 4 < < < 4 = 7 < 4 = 8 5 < 4 = # ! : 5 < 4 = % 5 < 4 = & 5 < 4 = ' > < ! system clocking and pipelining 4 5 6 # / 9 4 : 6 # 4 5 6 % < : 5 > < # % & ' ) * / ? @ - a 2 # % b 3 / ? 2 # % b 3 @ @ $ / 9 4 : 6 % 4 5 6 & 4 5 6 * / 9 4 : 6 * 4 5 6 + instruction fetching ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 18 march 11, 2010 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is se - lected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. device program counter program counter high byte pcl register ht56r22 pc10~pc8 pcl7~pcl0 ht56r23 pc11~pc8 ht56r24 pc12~pc8 ht56r25 pc13~pc8 HT56R26 pc14~pc8 the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable regis - ter. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data or program memory space, and is neither readable nor writeable. the acti - vated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or in - terrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a sub - routine or an interrupt routine, signaled by a return in - struction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. device stack levels ht56r22 6 ht56r23 ht56r24 ht56r25 HT56R26 12 if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in- struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec ! : 4 = < # 4 = < % 4 = < & 4 = < ! > c 4 = 4 = c 4 = ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 19 march 11, 2010 branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applica - tions which may be useful during debug or for products requiring frequent upgrades or program changes. structure the program memory has a capacity of 2k 14 to 32k 16. the program memory is addressed by the pro - gram counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. device capacity ht56r22 2k14 ht56r23 4k15 ht56r24 8k16 ht56r25 16k16 HT56R26 32k16 special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. reset vector this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. external interrupt 0/1 vector this vector is used by the external interrupt. if the ex - ternal interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. the external interrupt active edge transition type, whether high to low, low to high or both is specified in the intedge register. timer/event 0/1 counter interrupt vector this internal vector is used by the timer/event coun - ters. if a timer/event counter overflow occurs, the program will jump to its respective location and begin execution if the associated timer/event counter inter - rupt is enabled and the stack is not full. spi/i 2 c interrupt vector this internal vector is used by the spi/i 2 c interrupt. when either an spi or i 2 c bus, dependent upon which one is selected, requires data transfer, the program will jump to this location and begin execution if the spi/i 2 c interrupt is enabled and the stack is not full. ( ( ( ( b / 9 < ( : > ( : > : > a : > a : > a / 9 < > 5 < : > a # : > ( ( ( ' b ( ( ( b ( ( ( b ( ( # ( b ( ( # ' b ( ( # b / 9 < # : > # : > % : > / 9 < ( : > ( : > : > a : > a : > a / 9 < > 5 < : > a % : > a # : > / 9 < # : > # : > % : > / 9 < ( : > ( : > : > a : > a : > a / 9 < > 5 < : > a % : > a & : > a # : > / 9 < # : > # : > % : > / 9 < ( : > ( : > : > a : > a : > a / 9 < > 5 < : > a % : > a # : > / 9 < # : > # : > % : > / 9 < ( : > ( : > : > a : > a : > a / 9 < > 5 < : > a % : > a & : > a # : > / 9 < # : > # : > % : > + b b # ' # ) # * # * # * # b & b + b program memory structure ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 20 march 11, 2010 multifunction interrupt vector the multi-function interrupt vector is shared by sev - eral internal functions such as a time base overflow, a real time clock overflow, an a/d converter conver - sion completion, a falling edge appearing on the ex - ternal peripheral interrupt pin, a timer/event counter 2 or a timer/event counter 3 overflow, a spi data transfer completion. the program will jump to this lo - cation and begin execution if the relevant interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the following diagram illustrates the addressing/data flow of the look-up table: table program example the accompanying example shows how the table pointer and table data is defined and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org state - ment. the value at this org statement is 700h which refers to the start address of the last page within the 2k program memory of the ht56r22 microcontrollers. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be trans - ferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause er - rors if used again by the main routine. as a rule it is rec - ommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter- rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction table location bits b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc14 pc13 pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc14~pc8: current program counter bits @7~@0: table pointer tblp bits for the ht56r22, the table address location is 11 bits, i.e. from b10~b0. for the ht56r23, the table address location is 12 bits, i.e. from b11~b0. for the ht56r24, the table address location is 13 bits, i.e. from b12~b0. for the ht56r25, the table address location is 14 bits, i.e. from b13~b0. for the HT56R26, the table address location is 15 bits, i.e. from b14~b0. ! " ! # $ ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 21 march 11, 2010 table read program example: tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 706h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 705h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 700h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in- formation is stored. structure divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for cor - rect operation of the device. many of these registers can be read from and written to directly under program con - trol, however, some remain protected from user manipu - lation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. device capacity banks ht56r22 1288 0, 2 ht56r23 2568 0, 2 ht56r24 6408 0, 2~5 ht56r25 11528 0, 2~9 HT56R26 23048 0, 2~18 the two sections of data memory, the special purpose and general purpose data memory are located at con- secutive locations. all are implemented in ram and are 8 bits wide but the length of each memory section is dic- tated by the type of microcontroller chosen. the start ad - dress of the data memory for all devices is the address 00h . all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. for some devices, the data memory is subdivided into banks, which are selected using a bank pointer. only data in bank 0 can be directly addressed, data in bank 2~n must be indirectly addressed. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 22 march 11, 2010 = ( " < : > ! > 4 < : > ! + b ( ( ( b ( ( # b ( ( ' ( b & b = % = ( " < : > ! > 4 < : > ! b ( ( ( b ( ( # b ( ( ( b + b = % < % ) * < # % = ( " < : > ! > 4 < : > ! b ( ( ( b ( ( # b ( ( ( b + b = % f ) < * ' ( = ( " < : > ! > 4 < : > ! b ( ( ( b ( ( # b ( ( ( b + b = % f , < # # ) % = ( " < : > ! > 4 < : > ! b ( ( ( b ( ( # b ( ( ( b + b = % f # < % & ( ' data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the excep - tion of a few dedicated bits. the data memory can also be accessed through the memory pointer registers. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 23 march 11, 2010 special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory be - gins at the address 00h and are mapped into both bank 0 and bank 1. any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will re - turn a value of 00h . indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, al- though having their locations in normal ram register space, do not actually physically exist as normal regis- ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad- dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 with mp0 and iar1 with mp1 can together access data from the data memory. as the indirect ad - dressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are pro - vided. these memory pointers are physically imple - mented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to indirectly address and track data. mp0 can only be used to indirectly address data in bank 0 while mp1 can be used to address data in bank 0 and bank1. when any operation to the relevant indi - rect addressing registers is carried out, the actual ad - dress that the microcontroller is directed to, is the address specified by the related memory pointer. note that for the ht56r22 device, bit 7 of the memory pointers is not required to address the full memory space. when bit 7 of the memory pointers for this device is read, a value of 1 will be returned. note that indirect addressing using mp1 and iar1 must be used to access any data in bank 1. the following example shows how to clear a section of four data memory locations already de- fined as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory addresses. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 24 march 11, 2010 ( ( b ( # b ( % b ( & b ( ' b ( ) b ( * b ( + b ( b ( , b ( b ( b ( b ( b ( / b ( b # ( b # # b # % b # & b # ' b # ) b # * b # + b # b # , b # b # b # b # b # / b # b % ( b % # b % % b % & b % ' b % ) b % * b % + b % b % , b % b % b % b % b % / b % b & ( b & # b & % b & & b & ' b & ) b & * b & + b & b & , b & b & b & b & b & / b & b ' ( b + b @ : d a d g ( ( g ( ( # # b $ ( ( ( # # ( ( b # # b $ # % % b b 1 $ / " / ( # ( # ( # % b ( ( b ( # b ( % b ( & b ( ' b ( ) b ( * b ( + b ( b ( , b ( b ( b ( b ( b ( / b ( b # ( b # # b # % b # & b # ' b # ) b # * b # + b # b # , b # b # b # b # b # / b # b % ( b % # b % % b % & b % ' b % ) b % * b % + b % b % , b % b % b % b % b % / b % b & ( b & # b & % b & & b & ' b & ) b & * b & + b & b & , b & b & b & b & b & / b & b ' ( b ' # b ' % b ' & b ' ' b ' ) b ' * b ' + b ' b ' , b ) b + b ( ( b ( # b ( % b ( & b ( ' b ( ) b ( * b ( + b ( b ( , b ( b ( b ( b ( b ( / b ( b # ( b # # b # % b # & b # ' b # ) b # * b # + b # b # , b # b # b # b # b # / b # b % ( b % # b % % b % & b % ' b % ) b % * b % + b % b % , b % b % b % b % b % / b % b & ( b & # b & % b & & b & ' b & ) b & * b & + b & b & , b & b & b & b & b & / b & b ' ( b ' # b ' % b ' & b ' ' b ' ) b ' * b ' + b ' b ' , b ) b + b ( ( # # b $ ( ( ( # b # # ( ( b # # b $ # % % b & & b b 1 $ / " / ( # ( # ( # % % % b / / / $ ( ( # # b $ ( ( ( # b # # ( ( b # # b $ # % % b & & b b 1 $ / " / ( # ( # ( # % % % & & b / / " " / " $ special purpose data memory ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 25 march 11, 2010 accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per- mitted. when such operations are used, note that a dummy cycle will be inserted. bank pointer bp depending upon which device is used, the program and data memory is divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being ac - cessed irrespective of the value of the bank pointer. ac - cessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 76543210 ht56r22 ht56r23 dmbp1 dmbp0 ht56r24 dmbp2 dmbp1 dmbp0 ht56r25 pmbp0 dmbp3 dmbp2 dmbp1 dmbp0 HT56R26 pmbp1 pmbp0 dmbp4 dmbp3 dmbp2 dmbp1 dmbp0 bp registers list bp register ht56r22/ht56r23 bit76543210 name dmbp1 dmbp0 r/w r/w r/w por 00 bit7~2 unimplemented, read as 0 bit1~0 dmbp1 ~ dmbp0 : select data memory banks 00: bank 0 01: reserved 10: bank 2 11: undefined ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 26 march 11, 2010 ht56r24 bit76543210 name dmbp2 dmbp1 dmbp0 r/w r/w r/w r/w por 000 bit7~3 unimplemented, read as 0 bit2~0 dmbp2 ~ dmbp0 : select data memory banks 000: bank 0 001: reserved 010: bank 2 011: bank 3 100: bank 4 101: bank 5 110~111: undefined ht56r25 bit76543210 name pmbp0 dmbp3 dmbp2 dmbp1 dmbp0 r/w r/w r/w r/w r/w r/w por 00 bit7~2 unimplemented, read as 0 bit5 pmbp0 : select program memory banks 0: bank 0, program memory address is from 0000h ~ 1fffh 1: bank 1, program memory address is from 2000h ~ 3fffh bit4 unimplemented, read as 0 bit3 ~ 0 dmbp3 ~ dmbp0 : select data memory banks 0000: bank 0 0001: reserved 0010: bank 2 0011: bank 3 : : 1001: bank 9 1010~1111: undefined HT56R26 bit76543210 name pmbp1 pmbp0 dmbp4 dmbp3 dmbp2 dmbp1 dmbp0 r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit7~2 unimplemented, read as 0 bit6~5 pmbp1, pmbp0 : select program memory banks 00: bank 0, program memory address is from 0000h ~ 1fffh 01: bank 1, program memory address is from 2000h ~ 3fffh 10: bank 2, program memory address is from 4000h ~ 5fffh 11: bank 3, program memory address is from 6000h ~ 7fffh bit4 ~ 0 dmbp4 ~ dmbp0 : select data memory banks 00000: bank 0 00001: reserved 00010: bank 2 00011: bank 3 : : 10010: bank 18 10011~ 11111: undefined ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 27 march 11, 2010 status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the interrupt rou - tine can change the status register, precautions must be taken to correctly save it. note that bits 0~3 of the status register are both readable and writeable bits. input/output ports and control registers within the area of special function registers, the port pa, pb, etc data i/o registers and their associated con - trol register pac, pbc, etc play a prominent role. these registers are mapped to specific addresses within the data memory as shown in the data memory table. the data i/o registers, are used to transfer the appropriate output or input data on the port. the control registers specifies which pins of the port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program in - itialisation, it is important to first setup the control regis - ters to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating spe - cific bits of the i/o control registers during normal pro - gram operation is a useful feature of these devices. status register bit76543210 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 28 march 11, 2010 wake-up function register pawk when the microcontroller enters the idle/sleep mode, various methods exist to wake the device up and con - tinue with normal operation. one method is to allow a falling edge on the i/o pins to have a wake-up function. this register is used to select which port a i/o pins are used to have this wake-up function. pull-high registers papu, pbpu, pcpu, pdpu, pepu, pfpu, pgpu the i/o pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates the need for external pull-high resistors. this register selects which i/o pins are connected to internal pull-high resistors. software com register scomc the pins pb0~pb3 on port b can be used as scom lines to drive an external lcd panel. to implement this function, the scomc register is used to setup the cor - rect bias voltages on these pins. oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of configuration options and registers. system oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watch- dog timer and time base functions. external oscillators requiring some external components as well as a two fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. type name freq. pins external crystal hxt 400khz~ 12mhz osc1/ osc2 external rc erc 400khz~ 12mhz osc1 internal high speed rc hirc 4, 8 or 12mhz external low speed crystal lxt 32768hz xt1/ xt2* internal low speed rc lirc 32khz system clock configurations there are five system oscillators. three high speed os - cillators and two low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator - hxt, the external - erc, and the internal rc oscillator - hirc. the two low speed oscillator are the external 32768hz oscillator - lxt and the internal 32khz oscilla - tor - lirc. external crystal/resonator oscillator hxt the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feed - back for oscillation. however, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. crystal oscillator c1 and c2 values crystal frequency c1 c2 12mhz 8mhz 4mhz 1mhz 455khz (see note 2) 10pf 10pf note: 1. c1 and c2 values are for guidance only. 2. xtal mode configuration option: 455khz. 3. r p1 =5m ~10m is recommended. crystal recommended capacitor values # % c < 4 4 : ' ( % ' # ) * # ( ! + * , ( # % # $ @ # 6 > < < h : d 6 # d % h : d 6 % 6 < 5 : ! 5 5 e # % > 5 > 4 4 > 4 4 c : d + > 6 crystal/resonator oscillator hxt ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 29 march 11, 2010 external rc oscillator erc using the erc oscillator only requires that a resistor, with a value between 47k and 1.5m , is connected between osc1 and vdd, and a capacitor is connected between osc and ground, providing a low cost oscilla - tor configuration. it is only the external resistor that de - termines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to en - sure that the influence of the power supply voltage, tem - perature and process variations on the oscillation frequency are minimised. as a resistance/frequency ref - erence point, it can be noted that with an external 150k resistor connected and with a 5v voltage power supply and temperature of 25 degrees, the oscillator will have a frequency of 4mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pc0, leaving pin pc1 free for use as a normal i/o pin. internal rc oscillator hirc the internal rc oscillator is a fully integrated system os- cillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal fre - quency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 degrees, the fixed oscilla - tion frequency of 4mhz, 8mhz or 12mhz will have a tol - erance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pc1 and pc0 are free for use as nor - mal i/o pins. external 32768hz crystal oscillator lxt when the microcontroller enters the idle/sleep mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the power-down mode. to do this, another clock, independent of the system clock, must be provided. to do this a configuration option exists to allow a low speed oscillator, known as the lxt oscillator to be used. the lxt oscillator is implemented using a 32768hz crystal connected to pins. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value exter - nal capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. the external parallel feedback resistor, r p2 , is required. lxt oscillator c1 and c2 values crystal frequency c1 c2 32768hz 8pf 10pf note: 1. c1 and c2 values are for guidance only. 2. r p2 =5m~10m is recommended. 32768 hz crystal recommended capacitor values for the devices, a configuration option determines if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. if the i/o option is selected then the xt1/xt2 pins can be used as normal i/o pins. if the lxt oscillator is selected then the 32768hz crystal should be connected to the xt1/ xt2 pins. # # ' + ( > - ( % external rc oscillator erc ( # : d < $ @ < 4 < < # % ( # internal rc oscillator hirc < 4 4 : ' ( % ' # ) * # ( ! + * , ( # % % $ @ # 6 > a # d % h : d 6 % 6 < 5 : ! 5 5 e > 5 > 4 4 > 4 4 c : d + > 6 < 4 < < & % + * b i external lxt oscillator hxt ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 30 march 11, 2010 lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the qosc bit in the rtcc register. qosc bit lxt mode 0 quick start 1 low-power after power on the qosc bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. how - ever, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the qosc bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the appli - cation program sets the qosc bit high about 2 seconds after power-on. it should be noted that, no matter what condition the qosc bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low-power mode. internal low speed oscillator lirc when microcontrollers enter a power down condition, their internal clocks are normally switched off to stop microcontroller activity and to conserve power. how- ever, in many microcontroller applications it may be nec- essary to keep some internal functions operational, such as timers, even when the microcontroller is in the power-down mode. to do this, the device has a lirc oscillator, which is a fully integrated free running rc os - cillator with a typical period of 31.2 s at 5v, requiring no external components. it is selected via configuration op - tion. when the device enters the power down mode, the system clock will stop running, however the lirc oscil - lator will continue to run if selected to keep various inter - nal functions operational. system operating modes the devices have the ability to operate in several differ - ent modes. this range of operating modes, known as normal mode, slow mode, idle mode and sleep mode, allow the devices to run using a wide range of different slow and fast clock sources. the devices also possess the ability to dynamically switch between different clocks and operating modes. with this choice of operating functions users are provided with the flexibility to ensure they obtain optimal performance from the device ac - cording to their application specific requirements. clock sources in discussing the system clocks for the devices, they can be seen as having a dual clock mode. these dual clocks are what are known as a high oscillator and the other as a low oscillator. the high and low oscillator are the system clock sources and can be selected dy - namically using the hlclk bit in the clkmod register. the high oscillator has the internal name f m whose source is selected using a configuration option from a choice of either an external crystal/resonator, external rc oscillator or external clock source. the low oscillator clock source, has the internal name f sl , whose source is also selected by configuration op - tion. this internal f sl ,f m clock, is further modified by the slowc0~slowc2 bits in the clkmod register to provide the low frequency clock source f slow . an additional sub internal clock, with the internal name f sub , is a 32khz clock source which can be sourced from either lxt or lirc, selected by configuration option. to - gether with f sys /4, it is used as a clock source for certain internal functions such as the lcd driver, watchdog timer, buzzer, rtc interrupt and time base interrupt. the lcd clock source is the f sub clock source divided by 8, giving a frequency of 4khz. the internal clock f s ,is simply a choice of either f sub or f sys /4, using a configura- tion option. operating modes after the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the clkmod register. a combination of the hlclk and idlen bits in the clkmod register and use of the halt instruction determine in which mode the device will be run. the devices can operate in the follow - ing modes. normal mode f m on, f slow on, f sys =f m , cpu on, f s on, f wdt on/off de - pending upon the wdt configuration option and wdt control register. slow mode0 f m off, f slow =lxt or lirc, f sys =f slow , cpu on, f s on, f wdt on/off depending upon the wdt configuration op - tion and wdt control register. slow mode1 f m on, f slow =f m /2~f m /64, f sys =f slow , cpu on, f s on, f wdt on/off depending upon the wdt configuration option and wdt control register. idle mode f m ,f slow ,f sys off, cpu off; f sub on, f s on/off by selecting f sub or f sys /4, f wdt on/off depending upon the wdt configuration option and wdt control register. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 31 march 11, 2010 sleep mode f m ,f slow ,f sys ,f s , cpu off; f sub ,f wdt on/off depending upon the wdt configuration option and wdt control register. for all devices, when the system enters the sleep or idle mode, the high frequency system clock will always stop running. the accompanying tables shows the relation - ship between the clkmod bit, the halt instruction and the high/low frequency oscillators. the clmod bit can change normal or slow mode. + - $ % " ) ( % c ? < 4 # @ c ( @ c d < d # @ < ( @ d < b ! 5 4 < < d c < ! # @ : ( @ : e 4 < < d c < ! # @ : ( @ : 4 : : ! d < d # @ < ( @ d < c < 4 ( / $ b 1 b + ( # % c c c c * ' c & % c # * c c ' c % % ( ( ( ( # # # # # ( ( # # ( ( # # ( ( # ( # ( # ( # / % clock control register clkmod operating mode control operation mode description cpu f sys f sub normal mode on f m on slow0 mode on f sl on slow1 mode on f m /2~f m /64 on idle mode off off on sleep mode off off on/off ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 32 march 11, 2010 ! # $ ! . % e = : > b j g / $ g k ( b j g / $ g k # e = : > e = : > b j g / $ g k # b j g / $ g k ( e = : > g b 1 g g b 1 g / 0 / % 1 % ' . ) ( 2 % 3 % ' # 4 % . ) # 4 % * ! ' . ( ! ' 5 / 6 / 7 ( 2 % ( 2 % 8 9 ! : , ) ( 4 % 5 c a . a c ? k c % % 1 $ ! . % c c c a . l a c ? k c c . % $ ! . % c c c a . a c ? k c c ! ; $ ! . % c c c a . a c ? k c % f c * ' . m dual clock mode operation . c b 1 c ? c . c c < e < 4 = < ( . c & % 1 c ! : > # % c % a 6 6 6 c * ' a c . . c c ? ' c c ? ' c # # c < 4 = < 4 c ! : > c c k c : > a : > a : i i a e 4 < < & ' / b . . c / 9 < . c ! : > b ! 5 4 < < # % # % < / 9 < < 4 = < c c c ! : > / 9 < < 4 = # dual clock mode structure ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 33 march 11, 2010 mode switching the devices are switched between one mode and an - other using a combination of the hlclk bit in the clkmod register and the halt instruction. the hlclk bit chooses whether the system runs in either the nor - mal or slow mode by selecting the system clock to be sourced from either a high or low frequency oscillator. the halt instruction forces the system into either the idle or sleep mode, depending upon whether the idlen bit in clkmod register is set or not. when a halt instruction is executed and the idlen bit is not set. the system enters the sleep mode the follow - ing conditions exist: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt is enabled and clock source is selected from f sub . the wdt will stop if its clock source originates from the system clock or the wdt is disabled. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. this occurs be- cause when the device enters the power down mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi - nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. this also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors con - nected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be re- quired if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 34 march 11, 2010 each pin on port a can be setup via an individual config - uration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up oc - curs, the program will resume execution at the instruc - tion following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo- cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the watchdog timer counter overflows. watchdog timer operation the watchdog timer clock source is provided by the in - ternal clock, f s , which is in turn supplied by one of two sources selected by configuration option: f sub or f sys /4. note that if the watchdog timer configuration option has been disabled, then any instruction relating to its op - eration will result in no operation. most of the watchdog timer options, such as en - able/disable, watchdog timer clock source and clear in - struction type are selected using configuration options. in addition to a configuration option to enable the watch - dog timer, there are four bits, wdten3~ wdten0, in the misc register to offer an additional enable control of the watchdog timer. these bits must be set to a specific value of 1010 to disable the watchdog timer. any other values for these bits will keep the watchdog timer en - abled. after power on these bits will have the disabled value of 1010. one of the wdt clock sources is the internal f sub , which can be sourced from either the lxt or lirc. the lirc has an approximate period of 31.2 s at a supply voltage of 5v. however, it should be noted that this specified in - ternal clock period can vary with vdd, temperature and process variations. the lxt is supplied by an external 32768hz crystal. the other watchdog timer clock source option is the f sys /4 clock. whether the watchdog timer clock source is lirc, lxt or f sys /4, it is divided by 2 13 ~2 16 , using configuration option to obtain the required watchdog timer time-out period. the max time out pe- riod is when the 2 16 option is selected. this time-out pe- riod may vary with temperature, vdd and process variations. as the clear instruction only resets the last stage of the divider chain, for this reason the actual divi- sion ratio and corresponding watchdog timer time-out can vary by a factor of two. the exact division ratio de - pends upon the residual value in the watchdog timer counter before the clear instruction is executed. : 4 c ! : > < ! 4 # < ! % < ! # % : 4 c ? ' d c : 7 % # & c a % # ' c a % # ) c % # * c 8 % + 4 < c % c % # % a c % # & a c % # ' c % # ) c ! > . watchdog timer ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 35 march 11, 2010 $ + % " ) ( % + / $ ( ( / $ # ( f & > < d 4 d < e 5 4 5 d ! / < < / ( / $ & # / $ % / $ & / # / % / & / $ % ( / $ # # / $ ( ( d < < < < 5 < : watchdog timer software control misc if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the power down mode, then the instruction clock is stopped and the watchdog timer will lose its protecting purposes. for systems that operate in noisy environ - ments, using the lirc oscillator is strongly recom - mended. under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the power down mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. clearing the watchdog timer there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the watchdog timer. note that for this second op - tion, if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no ef - fect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 36 march 11, 2010 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek web site. / - < ( 6 , - ; ; note: t rstd is power-on delay, typical time=100ms power-on reset timing chart / + ( 6 # f # # ( = f # ( ( = - - ( 6 ( # l l - # $ ' # ' l & ( ( l note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 37 march 11, 2010 res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. low voltage reset lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected via configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during idle/sleep mode the watchdog time-out reset during idle/sleep mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst can be chosen to be either 1024 or 2 clock cycles via configuration option if the sys - tem clock source is provided by erc or hirc. the sst is 1024 for hxt or lxt. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the idle/sleep function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset uu res or lvr reset during normal or slow mode operation 1u wdt time-out reset during normal or slow mode operation 11 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack : < wdt time-out reset during idle/sleep timing chart / < ( 6 , - ( 6 ' - ; note: t rstd is power-on delay, typical time=100ms res reset timing chart - < ; note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart ; : < note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 38 march 11, 2010 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) mp0 xxx xxxx uuu uuuu uuu uuuu uuu uuuu mp1 xxx xxxx uuu uuuu uuu uuuu uuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu bp 00 00 00 uu 000 000 000 uuu 00 0000 00 0000 00 0000 uu uuuu 000 0000 000 0000 000 0000 uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu xxx xxxx uuu uuuu uuu uuuu uuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu rtcc 00 0111 00 0111 00 0111 uu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu lcdc 00 0000 00 0000 00 0000 uu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu 0000 1 0000 1 0000 1 uuuu u tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr3 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr3c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pawk 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu ht56r22 ht56r23 ht56r24 ht56r25 HT56R26 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 39 march 11, 2010 register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) pb 11 1111 11 1111 11 1111 uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 11 1111 11 1111 11 1111 uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 00 0000 00 0000 00 0000 uu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1 1111 1 1111 1 1111 u uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1 1111 1 1111 1 1111 u uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 111 111 111 uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 111 111 111 uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 000 000 000 uuu 0000 0000 0000 0000 0000 0000 uuuu uuuu pwm0l 0000 0 0000 0 0000 0 uuuu u pwm0h 0000 0000 0000 0000 0000 0000 uuuu uuuu pwm1l 0000 0 0000 0 0000 0 uuuu u pwm1h 0000 0000 0000 0000 0000 0000 uuuu uuuu intc1 0 0 0 0 0 0 u u 00 00 00 00 00 00 uu uu 000 000 000 000 000 000 uuu uuu adpcr 0000 0000 0000 0000 0000 0000 uuuu uuuu pwm2l 0000 0 0000 0 0000 0 uuuu u pwm2h 0000 0000 0000 0000 0000 0000 uuuu uuuu pwm3l 0000 0 0000 0 0000 0 uuuu u pwm3h 0000 0000 0000 0000 0000 0000 uuuu uuuu adrl xxxx xxxx xxxx uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 01 000 01 000 01 000 uuu uu acsr 11 000 11 000 11 000 uu uuu clkmod 0000 0x11 0000 0x11 0000 0x11 uuuu uuuu intedge 0000 0000 0000 uuuu spictl0 111 0 111 0 111 0 uuu u ht56r22 ht56r23 ht56r24 ht56r25 HT56R26 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 40 march 11, 2010 register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) spictl1 00 0000 00 0000 00 0000 uu uuuu spidr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu dactrl xxx 0 xxx 0 xxx 0 uuu u misc 0000 1010 0000 1010 0000 1010 uuuu uuuu mfic0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfic1 0 0 0 0 0 0 u u 00 00 00 00 00 00 uu uu 000 000 000 000 000 000 uuu uuu simctrl0 1110 000 1110 000 1110 000 uuuu uuu simctrl1 1000 0001 1000 0001 1000 0001 uuuu uuuu simdr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simar/ simctl2 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr2 xxxx xxxx xxxx xxxx xxxx xxxx uu u uuuu tmr2c 00 0 1000 00 0 1000 00 0 1000 uuuu uuuu tmr3 xxxx xxxx xxxx xxxx xxxx xxxx uu u uuuu tmr3c 00 0 1000 00 0 1000 00 0 1000 uuuu uuuu dal 0000 0000 0000 uuuu dah 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 11 1111 11 1111 11 1111 uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 11 1111 11 1111 11 1111 uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 00 0000 00 0000 00 0000 uu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu pf 1111 1111 1111 uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 0000 0000 uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu pg 11 11 11 uu pgc 11 11 11 uu pgpu 00 00 00 uu pinmap 0000 0000 0000 0000 0000 0000 uuuu uuuu note: - not implemented u means unchanged x means unknown ht56r22 ht56r23 ht56r24 ht56r25 HT56R26 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 41 march 11, 2010 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. most pins can have either an input or out - put designation under user program control. addi - tionally, as there are pull-high resistors and wake-up software configurations, the user is provided with an i/o structure to meet the needs of a wide range of applica - tion possibilities. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port ad - dress. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resis - tors, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via a register known as papu, pbpu, pcpu, pdpu, pepu, pfpu and pgpu located in the data memory. the pull-high resistors are implemented using weak pmos transistors. note that pin pc7 does not have a pull-high resistor selection. port a wake-up if the halt instruction is executed, the device will enter the idle/sleep mode, where the system clock will stop resulting in power being conserved, a feature that is im - portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the pa0~pa7 pins from high to low. after a halt instruc - tion forces the microcontroller into entering the idle/sleep mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that pins pa0 to pa7 can be selected individually to have this wake-up feature using an internal register known as pawk, lo - cated in the data memory. pawk, pac, papu, pbc, pbpu, pcc, pcpu, pdc, pdpu register ht56r22 register name por bit 76543210 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 pbc 3fh pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pcc 8fh pcc7 pcc3 pcc2 pcc1 pcc0 pcpu 00h pcpu3 pcpu2 pcpu1 pcpu0 pdc 07h pdc2 pdc1 pdc0 pdpu 00h pdpu2 pdpu1 pdpu0 unimplemented, read as 0 pawkn : pa wake-up function enable 0: disable 1: enable pacn/pbcn/pccn/pdcn : i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun : pull-high function enable 0: disable 1: enable ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 42 march 11, 2010 pawk, pac, papu, pbc, pbpu, pcc, pcpu, pdc, pdpu, pec, pepu, pfc, pfpu ht56r23/ht56r24 register name por bit 76543210 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu\7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 pbc ffh pbc7 pbc6 pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu 00h pcpu6 pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 pdc ffh pdc7 pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 pdpu 00h pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu2 pdpu1 pdpu0 pec 3fh pec5 pec4 pec3 pec2 pec1 pec0 pepu 00h pepu5 pepu4 pepu3 pepu2 pepu1 pepu0 pfc 0fh pfc3 pfc2 pfc1 pfc0 pfpu 00h pfpu3 pfpu2 pfpu1 pfpu0 unimplemented, read as 0 pawkn : pa wake-up function enable 0: disable 1: enable pacn/pbcn/pccn/pdcn/pecn/pfcn : i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun/pepun/pfpun : pull-high function enable 0: disable 1: enable ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 43 march 11, 2010 pawk, pac, papu, pbc, pbpu, pcc, pcpu, pdc, pdpu, pec, pepu, pfc, pfpu, pgc, pgpu ht56r25/HT56R26 register name por bit 76543210 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu\7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 pbc ffh pbc7 pbc6 pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu 00h pcpu6 pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 pdc ffh pdc7 pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 pdpu 00h pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu2 pdpu1 pdpu0 pec ffh pec7 pec6 pec5 pec4 pec3 pec2 pec1 pec0 pepu 00h pepu7 pepu6 pepu5 pepu4 pepu3 pepu2 pepu1 pepu0 pfc ffh pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 pfpu 00h pfpu7 pfpu6 pfpu5 pfpu4 pfpu3 pfpu2 pfpu1 pfpu0 pgc 03h pgc1 pgc0 pgpu 00h pgpu1 pgpu0 unimplemented, read as 0 pawkn : pa wake-up function enable 0: disable 1: enable pacn/pbcn/pccn/pdcn/pecn/pfcn/pgcn : i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun/pepun/pfpun/pgpun : pull-high function enable 0: disable 1: enable ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 44 march 11, 2010 i/o port control registers each port has its own control register, known as pac, pbc, pcc, pdc, pec, pfc and pgc which controls the input/output configuration. with this control register, each i/o pin with or without pull-high resistors can be re - configured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the out - put register. however, it should be noted that the pro - gram will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro- gram control. external interrupt input the external interrupt pin, int0/int1, are pin-shared with an i/o pins. to use the pins as external interrupt inputs the correct bits in the intc0 register must be programmed. the pin must also be setup as an input by setting bit in the port control register. a pull-high resistor can also be selected via the appropriate port pull-high resistor register. note that even if the pin is setup as an external interrupt input the i/o function still remains. external timer/event counter input the timer/event counter pins, tc0, tc1, tc2 and tc3 are pin-shared with i/o pins. for these shared pins to be used as timer/event counter inputs, the timer/event counter must be configured to be in the event counter or pulse width capture mode. this is achieved by setting the appropriate bits in the timer/event counter control register. the pins must also be setup as inputs by setting the appropriate bit in the port control register. pull-high resistor options can also be selected using the port pull-high resistor registers. note that even if the pin is setup as an exter - nal timer input the i/o function still remains. pfd output the pfd function output is pin-shared with an i/o pin. the output function of this pin is chosen using the configuration option. note that the corresponding bit of the port control register, must setup the pin as an output to enable the pfd output. if the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pfd function has been selected. pwm outputs the pwm function whose outputs are pin-shared with i/o pins. the pwm output functions are chosen using the pwmnl and pwmnh (n=0~3) registers. note that the corresponding bit of the port control registers, for the output pin, must setup the pin as an output to en - able the pwm output. if the pins are setup as inputs, then the pin will function as a normal logic input with the usual pull-high selections, even if the pwm regis - ters have enabled the pwm function. scom driver pins pins pb0~pb3 on port b can be used as lcd com driver pins. this function is controlled using the scomc register which will generate the necessary 1/2 bias signals on these four pins. a/d inputs each device in this series has eight inputs to the a/d converter. all of these analog inputs are pin-shared with i/o pins. if these pins are to be used as a/d inputs and not as i/o pins then the corresponding pcrn bits in the a/d converter control register, adpcr, must be properly setup. there are no configuration options as- sociated with the a/d converter. if chosen as i/o pins, then full pull-high resistor configuration options re- main, however if used as a/d inputs then any pull-high resistor configuration options associated with these pins will be automatically disconnected. pin remapping configuration the pin remapping function enables the function pins int0/1, tc0/1, pfd, pwm0/1/2 to be located on differ- ent port pins. it is important not to confuse the pin re - mapping function with the pin-shared function, these two functions have no interdependence. the pmap0~7 bit in the pinmap register allows the three function pins int0/1, tc0/1, pfd, pwm0/1/2 to be remapped to different port pins. after power up, these bits will be reset to zero, which will define the de - fault port pins to which these three functions will be mapped. changing this bit will move the functions to other port pins. examination of the pin names on the package diagrams will reveal that some pin function names are repeated, this indicates a function pin that can be remapped to other port pins. if the pin name is bracketed then this in - dicates its alternative location. pin names without brack - ets indicates its default location which is the condition after power-on. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 45 march 11, 2010 ht56r23/ht56r24/ht56r25/HT56R26 register name por bit 7 6 5 43210 pinmap 00h pmap7 pmap6 pmap5 pmap4 pmap3 pmap2 pmap1 pmap0 0: pd2/pwm2 1: pe5/[pwm2] 0 : pd1/pwm1 1: pd5/[pwm1] 0: pd0/pwm0 1: pd4/[pwm0] 0: pa7/tc1 1: pd6/[tc1] 0: pa6/int1 1: pd7/[int1] 0: pa5/tc0 1: pe2/[tc0] 0: pa4/int0 1: pe1/[int0] 0: pa3/pfd 1: pe0/[pfd] pinmap register . d ! < : < ! 5 > d < ! ! n 1 n n 1 n + / / c + < pc7 nmos input/output port - . = : > < 4 = : > d ! n 1 n 1 < : < ! 5 > d < ! ! > n n < = : < < : > : < < b ! 5 < 4 generic input/output ports ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 46 march 11, 2010 i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the user program, one of the first things to con- sider is port initialisation. after a reset, the i/o data reg- ister and i/o port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, are then programmed to setup some pins as outputs, these output pins will have an ini - tial high output value unless the associated port data register is first programmed. selecting which pins are in - puts and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. pins pa0 to pa7 each have a wake-up functions, se - lected via the pawk register. when the device is in the idle/sleep mode, various methods are available to wake the device up. one of these is a high to low transition of any of the these pins. single or multiple pins on port a can be setup to have this function. timer/event counters the provision of timers form an important part of any microcontroller , giving the designer a means of carrying out time related functions. the devices contain several 8-bit and 16-bit count-up timers. as each timer has three different operating modes, they can be configured to op- erate as a general timer, an external event counter or as a pulse width measurement device. the provision of a prescaler to the clock circuitry of the 8-bit timer/event counter also gives added range to this timer. there are two types of registers related to the timer/event counters. the first are the registers that contain the actual value of the timer/event counter and into which an initial value can be preloaded. reading from these registers retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer/event counter is to be used. the timer/event counters can have the their clock configured to come from an internal clock source. in addition, their clock source can also be configured to come from an external timer pin. # % & ' # % & ' d c < 4 = read modify write timing - . d ! < : < < b ! 5 < 4 : < ! 5 > d < ! ! ( ( f & & - % = : < < : > n 1 n n 1 n / $ / $ pb input/output port ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 47 march 11, 2010 configuring the timer/event counter input clock source the internal timer s clock can originate from various sources. the system clock source is used when the timer/event counter is in the timer mode or in the pulse width measurement mode. for the 8-bit timer/event counter this internal clock source is f sys which is also di - vided by a prescaler, the division ratio of which is condi - tioned by the timer control register, tmrnc, bits tnpsc0~tnpsc2. for the 16-bit timer/event counter this internal clock source can be chosen from a combi - nation of internal clocks using a configuration option and the tns bit in the tmrnc register. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tmr0, tmr1, tmr2 or tmr3 depending upon which timer is used. depending upon the condition of the tne bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. device all devices no. of 8-bit timers 3 timer name timer/event counter 0 timer/event counter 2 timer/event counter 3 timer register name tmr0 tmr2 tmr3 control register name tmr0c tmr2c tmr3c no. of 16-bit timers 1 timer name timer/event counter 1 timer register name tmr1l/tmr1h control register name tmr1c timer registers tmr0, tmr1l/tmr1h, tmr2, tmr3 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. for the 8-bit timer/event counters, these registers are known as tmr0, tmr2 or tmr3. for the 16-bit timer/event counter, a pair of regis - ters are required and are known as tmr1l/tmr1h. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition oc - curs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer or ffffh for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. to achieve a maximum full range count of ffh for the 8-bit timer or ffffh for the 16-bit timer, the preload reg - isters must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. however, if the timer/event counter is enabled and counting, any new data written into the preload data registers during this period will re - main in the preload registers and will only be written into the timer registers the next time an overflow occurs. for the 16-bit timer/event counter which has both low byte and high byte timer registers, accessing these reg - isters is carried out in a specific way. it must be noted when using instructions to preload data into the low byte timer register, the data will only be placed in a low byte buffer and not directly into the low byte timer register. the actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely tmr1h, is executed. on the other hand, using instructions to preload data into the high byte timer register will result in the data be- ing directly written to the high byte timer register. at the same time the data in the low byte buffer will be trans- ferred into its associated low byte timer register. for this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. af - ter this has been done, the low byte timer register can be read in the normal way. note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual con - tents of the low byte timer register. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 48 march 11, 2010 / : d < $ < d ! / : : < d c < e : > % + ! 4 < % f ( 7 # # f # # % 8 / : # ( c ? ( / < < c c c ! : > 8-bit timer/event counter structure / / : d < # * < d ! : < d c < e : > e : c c # ( $ b ! 5 e # * / : # % . c ? ' . c / 9 < & % + * b i < & % 1 $ c ! : > < < c c c ! : > 16-bit timer/event counter structure . ( # c ! : > $ ' + % " ) ( % ' < = = + / : 4 d ! < 4 # @ 4 : c < < ! d ! ( @ 4 : ! d ! / $ ( # > 4 < < 4 % ( ( ( ( # # # # ( % # ( # ( ( # # ( ( # # ( ( # ( # ( # ( # # @ # # @ % # @ ' # @ # @ # * # @ & % # @ * ' # @ # % / : 4 : ! < # @ < ( @ d < > ! d < 4 # ( ( # # ( ( # ( # d < < 4 : d d > : < e d 5 : d : < d 5 : 4 d ! < 4 # @ 4 : ! ! d ! a > c < < ! d ! ( @ 4 : ! c < < ! d ! a > ! d ! $ > < d a d g ( g timer/event counter control register tmrnc ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 49 march 11, 2010 + / $ ( # ( $ ' + % " ) ( % ' < $ > < d a d g ( g / : 4 d ! < 4 # @ 4 : c < < ! d ! ( @ 4 : ! d ! : < d 5 : 4 d ! < 4 # @ 4 : ! ! d ! a > c < < ! d ! ( @ 4 : ! c < < ! d ! a > ! d ! / : 4 : ! < # @ < ( @ d < # ( ( # # ( ( # ( # d < < 4 : d d > : < e d 5 : d > ! d < 4 4 < 4 = : 4 # @ c 7 & % + * b i & % 1 8 ( @ c ? ' timer/event counter control register tmrnc timer control registers tmr0c, tmr1c, tmr2c, tmr3c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. it is the timer control register together with its corre- sponding timer registers that control the full operation of the timer/event counters. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to en - sure its correct operation, a process that is normally car - ried out during program initialisation. to choose which of the three modes the timer is to oper - ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding timer control register, which are known as the bit pair tnm1/tnm0, must be set to the re - quired logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, depending upon which timer is used, provides the basic on/off con- trol of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. for timers that have prescalers, bits 0~2 of the timer con- trol register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width measurement mode, the ac - tive transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tne. an additional t1s bit in the 16-bit timer/event counter control register is used to deter - mine the clock source for the timer/event counter. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 50 march 11, 2010 tmr0c register bit76543210 name t0m1 t0m0 t0on t0eg t0psc2 t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 01000 bit 7,6 t0m1, t0m0 : timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 not implemented, read as 0 bit 4 t0on : timer/event counter counting enable 0: disable 1: enable bit 3 t0eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 t0psc2, t0psc1, t0psc0 : timer prescaler rate selection timer internal clock= 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 51 march 11, 2010 tmr1c register ht56r22 bit76543210 name t1m1 t1m0 t1on t1eg t1psc2 t1psc1 t1psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 01000 bit 7,6 t1m1, t1m0 : timer1 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 not implemented, read as 0 bit 4 t1on : timer/event counter counting enable 0: disable 1: enable bit 3 t1eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 t1psc2, t1psc1, t1psc0 : timer prescaler rate selection timer internal clock= 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 52 march 11, 2010 tmr1c register ht56r23/ht56r24/ht56r25/HT56R26 bit76543210 name t1m1 t1m0 t1s t1on t1eg r/w r/w r/w r/w r/w r/w por00001 bit 7,6 t1m1, t1m0 : timer 1 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 t1s : timer clock source 0: f sys /4 1: lxt oscillator bit 4 t1on : timer/event counter counting enable 0: disable 1: enable bit 3 t1eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 unimplemented, read as 0 tmr2c register bit76543210 name t2m1 t2m0 t2on t2eg t2psc2 t2psc1 t2psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 01000 bit 7, 6 t2m1, t2m0 : timer 2 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 unimplemented, read as 0 bit 4 t2on : timer/event counter counting enable 0: disable 1: enable bit 3 t2eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 t2psc2, t2psc1, t2psc0 : timer prescaler rate selection timer internal clock= 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 53 march 11, 2010 tmr3c register ht56r25/26 bit76543210 name t3m1 t3m0 t3on t3eg t3psc2 t3psc1 t3psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 01000 bit 7, 6 t3m1, t3m0 : timer 3 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 unimplemented, read as 0 bit 4 t3on : timer/event counter counting enable 0: disable 1: enable bit 3 t3eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 t3psc2, t3psc1, t3psc0 : timer prescaler rate selection timer internal clock= 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 54 march 11, 2010 timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal inter - rupt signal each time the timer/event counter over - flows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control regis - ter must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock is used as the timer clock. the timer input clock source is either f sys ,f sys /4 or the lxt oscillator. however, this timer clock source is fur - ther divided by a prescaler, the value of which is deter - mined by the bits tnpsc2~tnpsc0 in the timer control register. the timer-on bit, tnon must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value al - ready loaded into the preload register and continue counting. a timer overflow condition and corresponding internal interrupt is one of the wake-up sources, how - ever, the internal interrupts can be disabled by ensuring that the tne bits of the intcn register are reset to zero. event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tcn pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode, the external timer tcn pin, is used as the timer/event counter clock source, however it is not di - vided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tneg, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the tneg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event coun - ter will reload the value already loaded into the preload register and continue counting. the interrupt can be dis - abled by ensuring that the timer/event counter inter - rupt enable bit in the corresponding interrupt control register, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the idle/sleep mode, the timer/event counter will continue to record externally changing logic events on the timer input tcn pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. pulse width capture mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex- ternal timer pin. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width capture mode bit7 bit6 11 in this mode the internal clock, f sys ,f sys /4 or the lxt, is used as the internal clock for the 8-bit timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits 4 < < 4 < : > : ; # ; % ; $ ; $ ; # timer mode timing chart ; % / 9 < / 4 : ; & ; # event counter mode timing chart (tneg=1) ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 55 march 11, 2010 tnpsc2~tnpsc0, which are bits 2~0 in the timer con - trol register. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to en - able the timer/event counter, however it will not actu - ally start counting until an active edge is received on the external timer pin. if the active edge select bit tneg, which is bit 3 of the timer control register, is low, once a high to low transi - tion has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will be- gin counting once a low to high transition has been re- ceived on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is im- portant to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the exter- nal control signal on the external timer pin returns to its original level, whereas in the other two modes the en - able bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tcn pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width capture until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is gener - ated and the timer/event counter will reload the value al - ready loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corre - sponding interrupt control register, is reset to zero. as the tcn pin is shared with an i/o pin, to ensure that the pin is configured to operate as a pulse width capture pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width capture mode, the second is to ensure that the port control register configures the pin as an input. prescaler bits tnpsc0~tnpsc2 of the tmrnc register can be used to define a division ratio for the internal clock source of the timer/event counter enabling longer time out periods to be setup. programmable frequency divider pfd the programmable frequency divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. the pfd output is pin-shared with the i/o pin pa3. the pfd function is selected via configuration option, how- ever, if not selected, the pin can operate as a normal i/o pin. the clock source for the pfd circuit can originate from either timer/event counter 0 or timer/event counter 1 overflow signal selected via configuration option. the output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. the timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the pfd output to change state. the timer will then be auto - matically reloaded with the preload register value and continue counting-up. for the pfd output to function, it is essential that the corre - sponding bit of the port a control register pac bit 3 is setup as an output. if setup as an input the pfd output will not function, however, the pin can still be used as a normal in - put pin. the pfd output will only be activated if bit pa3 is set to 1 . this output data bit is used as the on/off control bit for the pfd output. note that the pfd output will be low if the pa3 output data bit is cleared to 0 . using this method of frequency generation, and if a crystal oscillator is used for the system clock, very pre - cise values of frequency can be generated. bits tnpsc0~tnpsc2 of the control register can be used to define the pre-scaling stages of the internal clock source of the timer/event counter. the ; # ; % ; & ; ' / 9 < > : $ e 5 / k ( 4 < : > : 4 : 4 < : > : > < d c < < ! d ! c # 6 pulse width capture mode timing chart (tne=0) ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 56 march 11, 2010 timer/event counter overflow signal can be used to generate signals for the pfd and timer interrupt. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be configured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respec - tive internal interrupt vector. for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the in - ternal timer clock, the microcontroller will only see this ex - ternal event when the next timer clock pulse arrives. as a result, there may be small differences in measured val - ues requiring programmers to take this into account dur - ing programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the inter - nal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly in - itialised before using them for the first time. the associ - ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control regis - ter must also be correctly set to ensure the timer is prop - erly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg - isters are unknown. after the timer has been initialised the timer can be turned on and off by controlling the en - able bit in the timer control register. when the timer/event counter overflows, its corre- sponding interrupt request flag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are en- abled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overflow occurs the de - vice will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer inter - rupt request flag should first be set high before issuing the halt instruction to enter the idle/sleep mode. timer program example the program shows how the timer/event counter regis - ters are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. c < e < 4 = # : > : # pfd function ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 57 march 11, 2010 pfd programming example org 04h ; external interrupt vector org 08h ; timer counter 0 interrupt vector jmp tmr0int ; jump here when timer 0 overflows :: org 20h ; main program :: ;internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ;setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a :: set tmr0c.4 ; start timer 0 :: time base the device includes a time base function which is used to generate a regular time interval signal. the time base time interval magnitude is determined using an internal 12~15 stage counter which sets the division ra- tio of the clock source. this division ratio is controlled by the time base divider configuration option. the clock source is selected using a peripheral clock configuration option. when the time base times out, a time base interrupt signal will be generated. it should be noted that as the time base clock source is the same as the timer/event counter clock source, care should be taken when programming. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 58 march 11, 2010 pulse width modulator the devices contains a series of pulse width modulation, pwm, outputs. useful for such applications such as motor speed control, the pwm function provides an output with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register. part no. channels pwm mode output pin register names all devices 4 8+4 pd0~ pd3 pwm0l~ pwm3l pwm0h~ pwm3h pwm overview a register pair, located in the data memory is assigned to each pulse width modulator output and are known as the pwm registers. it is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. the pwm registers also contain the enable/dis - able control bit for the pwm outputs. to increase the pwm modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. note that it is only necessary to write the required modulation value into the corresponding pwm register as the subdivision of the waveform into its sub-modulation cycles is imple- mented automatically within the microcontroller hard- ware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation fre - quency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 12-bits wide, the overall pwm cycle frequency is f sys /4096. however, when in the 8+4 mode of operation, the pwm modulation frequency will be f sys /256. pwm modulation frequency pwm cycle frequency pwm cycle duty f sys /256 f sys /4096 (pwm register value)/4096 8+4 pwm mode modulation each full pwm cycle, as it is 12-bits wide, has 4096 clock periods. however, in the 8+4 pwm mode, each pwm cy - cle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as i in the table. each one of these sixteen sub-cycles con - tains 256 clock cycles. in this mode, a modulation fre - quency increase of sixteen is achieved. the 12-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit4~bit11 is denoted here as the dc value. the second group which consists of bit0~bit3 is known as the ac value. in the 8+4 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~15) dc (duty cycle) modulation cycle i (i=0~15) iac dc+1 256 iac dc 256 8+4 mode modulation cycle values the accompanying diagram illustrates the waveforms associated with the 8+4 mode of pwm operation. it is important to note how the single pwm cycle is subdi- vided into 16 individual modulation cycles, numbered 0~15 and how the ac value is related to the pwm value. pwm output control the four pwm0~pwm3 outputs are shared with pins pd0~pd3. to operate as a pwm output and not as an i/o pin, bit 0 of the relevant pwm register bit must be set high. a zero must also be written to the corresponding bit in the pdc port control register, to ensure that the pwm0 output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm 12-bit value has been written into the pwm register pair register, writing a 1 to the corre - sponding pd data register will enable the pwm data to appear on the pin. writing a 0 to the bit will disable the pwm output function and force the output low. in this way, the port d data output register bits, can also be used as an on/off control for the pwm function. note that if the enable bit in the pwm register is set high to enable the pwm function, but a 1 has been written to its corresponding bit in the pdc control register to con - figure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 59 march 11, 2010 pwm programming example the following sample program shows how the pwm output is setup and controlled. mov a,64h ; setup pwm0 value to 1600 decimal which is 640h mov pwm0h,a ; setup pwm0h register value clr pwm0l ; setup pwm0l register value clr pdc.0 ; setup pin pd0 as an output set pwm0en ; set the pwm0 enable bit set pd.0 ; enable the pwm0 output :: :: clr pd.0 ; pwm0 output disabled pd0 will remain low 3 $ % " ) ( % ) ' < > + ( c c < # @ < ( @ > < $ > < d a d g ( g - < : ( f & - < : ' f # # / $ ( & #% + ( # # ,# ( + * ) ' ( f & e ! ( b f & b b ! 5 ! pwm register pairs c ? % 2 3 k # * ( ( 2 3 k # * ( # 2 3 k # * ( % 2 3 k # * # ) 4 4 < @ ' ( , * c ? # ( ( % ) * # ( # % ) * # ( # % ) * # ( # % ) * d : < 4 4 < ( d : < > d @ % ) * c ? d : < 4 4 < # d : < 4 4 < % d : < 4 4 < # ) d : < 4 4 < ( # ( ( % ) * # ( ( % ) * # ( ( % ) * # ( # % ) * # ( ( % ) * # ( # % ) * # ( # % ) * # ( # % ) * # ( ( % ) * # ( ( % ) * # ( ( % ) * # ( ( % ) * # ( ( % ) * # ( # % ) * # ( # % ) * # ( # % ) * 8+4 pwm mode ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 60 march 11, 2010 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d con - version electronic circuitry into the microcontroller , the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the device contains an 8-channel analog to digital con - verter which can directly interface to external analog sig - nals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit dig - ital value. the accompanying block diagram shows the overall in - ternal structure of the a/d converter, together with its as - sociated registers. a/d converter data registers adrl, adrh the device, which has an internal 12-bit a/d converter, requires two data registers, a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digit- ised conversion value. only the high byte register, adrh, utilises its full 8-bit contents. the low byte regis- ter utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d data registers a/d converter control registers adcr, acsr, adpcr to control the function and operation of the a/d con - verter, three control registers known as adcr, acsr and adpcr are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of con - version status. the acs2~acs0 bits in the adcr register define the channel number. as the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register to determine which analog channel is actually connected to the internal a/d converter. the adpcr control register contains the pcr7~pcr0 bits which determine which pins on pa7~pa0 are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if pcr7~pcr0 has a value of 11111111 , then all eight pins, namely an7~an0 will all be set as analog inputs. note that if the pcr7~pcr0 bits are all set to zero, then all the pa7~pa0 pins will be setup as normal i/os. < 4 = d $ ! b ! ( f % / ! 5 < < 4 / d c $ / < c ? ( $ ( # $ # * $ * + $ + a/d converter structure ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 61 march 11, 2010 adrh, adrl register adrh adrl bit7654321076543210 name d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrrrrrr porxxxxxxxxxxxx x unknown unimplemented, read as 0 d11~d0 : adc conversion data adcr register bit76543210 name start eocb acs2 acs1 acs0 r/w r/w r r/w r/w r/w por 0 1 000 bit 7 start : start the a/d conversion 01 0 : start 0 1 : reset the a/d converter and set eocb to 1 bit 6 eocb : end of a/d conversion flag 0: a/d conversion ended 1: a/d conversion in progress bit 5~3 unimplemented, read as 0 bit 2~0 acs2~acs0 : select a/d channel 000 an0 001 an1 010 an2 011 an3 100 an4 101 an5 110 an6 111 an7 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 62 march 11, 2010 adpcr register bit76543210 name pcr7 pcr6 pcr5 pcr4 pcr3 pcr2 pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w porx0000000 x unknown port pa - a/d converter input pin selection bit 7 pcr7 : pa7 or an7 0: pa7 i/o pin or other pin-shared function 1: an7 a/d converter input bit 6 pcr6 : pa6 or an6 0: pa6 i/o pin or other pin-shared function 1: an6 a/d converter input bit 5 pcr5 : pa5 or an5 0: pa5 i/o pin or other pin-shared function 1: an5 a/d converter input bit 4 pcr4 : pa4 or an4 0: pa4 i/o pin or other pin-shared function 1: an4 a/d converter input bit 3 pcr3 : pa3 or an3 0: pa3 i/o pin or other pin-shared function 1: an3 a/d converter input bit 2 pcr2 : pa2 or an2 0: pa2 i/o pin or other pin-shared function 1: an2 a/d converter input bit 1 pcr1 : pa1 or an1 0: pa1 i/o pin or other pin-shared function 1: an1 a/d converter input bit 0 pcr0 : pa0 or an0 0: pa0 i/o pin or other pin-shared function 1: an0 a/d converter input acsr register bit76543210 name test adonb adcs2 adcs1 adcs0 r/w r/w r/w r/w r/w r/w por 1 0 000 bit 7 test : for test mode use only bit 6 adonb : adc module power on/off control bit 0: adc module power on 1: adc module power off note: 1. it is recommended to set adonb=1 before entering idle/sleep to reduce power consumption 2. adonb=1 will power down the adc module. bit 5~3 unimplemented, read as 0 bit 2~0 adcs2~adcs0 : select a/d converter clock source 000: system clock/2 001: system clock/8 010: system clock/32 011: undefined, can t be used. 100: system clock 101: system clock/4 110: system clock/16 111: undefined, can t be used. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 63 march 11, 2010 the start bit in the register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to a 1 and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is com - plete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the inter - rupts are enabled, an appropriate internal interrupt sig - nal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d inter - nal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detect - ing the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs2, adcs1 and adcs0 bits in the acsr register. controlling the power on/off function of the a/d con- verter circuitry is implemented using the value of the adonb bit. although the a/d clock source is determined by the sys- tem clock f sys , and by bits adcs2, adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad ,is0.5 s, care must be taken for system clock speeds in excess of 4mhz. for system clock speeds in excess of 4mhz, the adcs2, adcs1 and adcs0 bits should not be set to 000 . doing so will give a/d clock periods that are less than the mini - mum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for exam - ples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum a/d clock period. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a. bits pcr7~pcr0 in the adpcr reg - ister, determine whether the input pins are setup as nor - mal port a input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resis - tors, which are setup through register programming, ap - ply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not neces - sary to first setup the a/d pin as an input in the pac port control register to enable the a/d input as when the pcr7~pcr0 bits enable an a/d input, the status of the port control register will be overridden. f sys a/d clock period (t ad ) adcs2, adcs1, adcs0=000 (f sys /2) adcs2, adcs1, adcs0=001 (f sys /8) adcs2, adcs1, adcs0=010 (f sys /32) adcs2, adcs1, adcs0=100 (f sys) adcs2, adcs1, adcs0=101 (f sys /4) adcs2, adcs1, adcs0=110 (f sys /16) adcs2, adcs1, adcs0=011, 111 1mhz 2s8 s32 s1 s4 s16 s undefined 2mhz 1s4 s16 s 500ns 2s8 s undefined 4mhz 500ns 2s8 s 250ns* 1s4 s undefined 8mhz 250ns* 1s4 s 125ns* 500ns 2s undefined 12mhz 167ns* 667ns 2.67s 83ns* 333ns* 1s undefined a/d clock period examples ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 64 march 11, 2010 summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d con - version process. step 1 select the required a/d conversion clock by correctly programming bits adcs2, adcs1 and adcs0 in the register. step 2 select which pins are to be used as a/d inputs and configure them as a/d input pins by correctly program - ming the pcr7~pcr0 bits in the adpcr register. step 3 enable the a/d by clearing the adonb in the acsr register to zero. step 4 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the reg - ister. step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, in the intc0 interrupt control register must be set to 1 , the multi-function interrupt enable bit, emfi, in the intc1 register and the a/d converter interrupt bit, eadi, in the intc1 register must also be set to 1 . step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr regis- ter from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0 . step 7 to check when the analog to digital conversion pro - cess is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the in - terrupts are enabled and the stack is not full, the pro - gram can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the vari - ous stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter func - tion is fully under the control of the application program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period. programming considerations when programming, special attention must be given to the pcr7~pcr0 bits in the adpcr register. if these bits are all cleared to zero no external pins will be se - lected for use as a/d input pins allowing the pins to be used as normal i/o pins. setting the adonb bit high has the ability to power down the internal a/d circuitry, which may be an important consideration in power sensitive applications. the adonb bit should be set high before entering any of the low power operating modes or be - fore a halt instruction is executed to reduce power consumption. a/d transfer function as the device contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the vdd voltage, this gives a single bit analog input value of v dd /4096. the diagram show the ideal transfer function between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 0.5 lsb off - set is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 65 march 11, 2010 example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and turn on adonb bit mov a,00100000b ; setup adcr register to configure port pb0~pb3 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the ; following start ; signal (0-1-0) must be issued ; instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next a/d conversion example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and turn on adonb bit mov a,00100000b ; setup adcr register to configure port pb0~pb3 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d : ; as the port b channel bits have changed the ; following start signal(0-1-0) must be issued ; : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emfi ; enable multi-function interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_: mov acc_stack,a ; save acc to user defined memory a,status mov status_stack,a ; save status to user defined memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : exit__isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory clr adf ; clear adc interrupt flag reti ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 66 march 11, 2010 4 ( ( ( 9 9 9 9 9 9 2 % @ ( 3 h : < g ( g ( # ( / % f ( % f ( e / d c 4 # @ c > 4 c ! : % @ < 4 < ! 4 5 < 4 < 4 = : c a c ? % a c ? ' a c ? a c ? # * c ? & % k ' k # * $ @ c 4 4 > < ! ( ( ( c 4 4 ( ( # c 4 4 / d c 4 > < ! d : < $ $ c c $ % 4 a/d conversion timing / b 7 8 : < b b ( & b ( % b ( # b ( 6 ) ( # % & ' ( , & ' ( , ' ' ( , ) ' ( , * < ! > : - < ! # 6 ) - ' ( , * ideal a/d transfer function ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 67 march 11, 2010 serial interface function the device contains a serial interface function, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of commu - nication with external peripheral hardware. having rela - tively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim in - terface function must first be selected using a configura - tion option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using a bit in an internal register. spi interface the spi interface is often used to communicate with ex - ternal peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple commu - nication protocol simplifying the programming require - ments when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the mcu can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, here, as only a single select pin, scs , is provided only one slave device can be connected to the spi bus. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by selecting the sim enable con - figuration option and setting the correct bits in the simctl0/simctl2 register. after the spi configura - tion option has been configured it can also be addi - tionally disabled or enabled using the simen bit in the simctl0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations be - ing implemented by the master. the master also con - trols the clock signal. as the device only contains a single scs pin only one slave device can be utilised. the spi function in this device offers the following fea- tures: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge wcol and csen bit enabled or disable select $ # ) ( % # ? % 1 1 spi master/slave connection : 9 9 5 c ! : : c ! : > < ! / < < < ! < 4 = / d ! < < < 4 = : 4 < 4 c ? c / : 1 c ! : > / $ / < < 1 / " 1 spi block diagram ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 68 march 11, 2010 the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of cer - tain control bits such as csen, simen and scs .in the table i, z represents an input floating condition. there are several configuration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. another two sim configuration options determine if the csen and wcol bits are to be used. configuration option function sim function sim interface or i/o pins spi csen bit enable/disable spi wcol bit enable/disable spi interface configuration options spi registers there are three internal registers which control the over - all operation of the spi interface. these are the simdr data register and two control registers simctl0 and simctl2. note that the simctl1 register is only used by the i 2 c interface. the simdr register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the microcontroller writes data to the spi bus, the actual data to be transmitted must be placed in the simdr reg- ister. after the data is received from the spi bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the spi bus must be made via the simdr register. bit76543210 label sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxxx there are also two control registers for the spi inter - face, simctl0 and simctl2. note that the simctl2 register also has the name simar which is used by the i 2 c function. the simctl1 register is not used by the spi function, only by the i 2 c function. register simctl0 is used to control the enable/disable function and to set the data transmission clock frequency. al - though not connected with the spi function, the simctl0 register is also used to control the peripheral clock prescaler. register simctl2 is used for other control functions such as lsb/msb selection, write colli - sion flag etc. the following gives further explanation of each simctl1 register bit: simidle the simidle bit is used to select if the spi interface continues running when the device is in the idle mode. setting the bit high allows the spi interface to maintain operation when the device is in the idle mode. clearing the bit to zero disables any spi opera - tions when in the idle mode. this spi/i 2 c idle mode control bit is located at clkmod register bit4. simen the bit is the overall on/off control for the spi inter - face. when the simen bit is cleared to zero to disable the spi interface, the sdi, sdo, sck and scs lines will be in a floating condition and the spi operating current will be reduced to a minimum value. when the bit is high the spi interface is enabled. the sim config- uration option must have first enabled the sim inter- face for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condi- tion and should therefore be first initialised by the ap- plication program. sim0~sim2 these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selec - tion and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the timer/event counter. if the spi slave mode is selected then the clock will be supplied by an external master device. pin master/salve simen=0 master simen=1 slave simen=1 csen=0 csen=1 csen=0 csen=1 scs =0 csen=1 scs =1 scs zzlzi , zi , z s d ozooooz sdi z i, z i, z i, z i, z z sck z h: ckpol=0 l: ckpol=1 h: ckpol=0 l: ckpol=1 i, z i, z z note: z floating, h output high, l output low, i input, o output level, i,z input floating (no pull-high) spi interface pin status ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 69 march 11, 2010 $ + - % " ) ( % $ > < d a d o ( g % c 4 < # @ < ( @ d < > 5 < < 4 = < d 4 d < e 5 % < d < 4 = < % # ( ( / $ a c ? ' a c ? # * a c ? * ' a c a / : ( : > : % < % d $ : d ( ( ( ( # # # # ( ( # # ( ( # # + # ( % ( # ( # ( # ( # 1 / $ 1 # 1 ( spi/i 2 c control register simctl0 $ + - % " ) ( % + 4 4 > < c < ! # @ c 5 d ( @ > ! 4 < < c < ! # @ 4 < < ( @ 4 < < > < # @ < ( @ c < ! 5 c d # @ ( @ < 4 = / d ! < 4 # @ 9 ( @ 9 < 4 = < # @ 9 ( @ 9 $ > < d a d g ( g ( / $ 1 / " 1 spi control register simctl2 $ + - % " ) ( % + 4 4 = e < d ! c < ! # @ 4 = e < d ! d ( @ 4 = e < d ! d $ > < d a d g ( g d d e h : c < ! # @ h : d d ( @ h : d e 4 = e < d ! c < ! # @ d o 4 = e < d ! ( @ 4 = e < d ! 4 d # @ d ( @ 4 d % : : c < ! # @ : ( @ : < < ! d d 4 5 d c < ! # @ 4 5 d ( @ 4 5 d c c < ! # @ c 4 > < ( @ c 4 > < ( b . . 1 . 1 b b b i 2 c control register simctl1 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 70 march 11, 2010 sim0 sim1 sim2 spi master/slave clock control and i2c enable 0 0 0 spi master, f sys /4 0 0 1 spi master, f sys /16 0 1 0 spi master, f sys /64 0 1 1 spi master, f sub 100 spi master timer/event counter 0 output/2 1 0 1 spi slave 110i 2 c mode 1 1 0 not used spi control register simctl2 the simctl2 register is also used by the i 2 c interface but has the name simar . trf the trf bit is the transmit/receive complete flag and is set high automatically when an spi data transmis - sion is completed, but must be cleared by the applica - tion program. it can be used to generate an interrupt. wcol the wcol bit is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simdr register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via configu- ration option. csen the csen bit is used as an on/off control for the scs pin. if this bit is low then the scs pin will be disabled and placed into a floating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or en - abled via configuration option. mls this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. ckeg and ckpol these two bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data trans - fer is executed otherwise an erroneous clock edge may be generated. the ckpol bit determines the base condition of the clock line, if the bit is high then the sck line will be low when the clock is inactive. when the ckpol bit is low then the sck line will be high when the clock is inactive. the ckeg bit deter - mines active clock edge type which depends upon the condition of ckpol . ckpol ckeg sck clock signal 00 high base level active rising edge 01 high base level active falling edge 10 low base level active falling edge 11 low base level active rising edge spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simdr register, transmission/reception will begin si - multaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simdr register will be transmitted and any data on the sdi pin will be shifted into the simdr regis - ter. the master should output an scs signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled be - fore/after an scs signal is received. the spi will continue to function even after a halt in- struction has been executed. i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data trans- fer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this rea - son it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and re - ceived on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 71 march 11, 2010 1 7 1 k # 8 1 7 1 k ( 8 > : + ( * # ) % ' & & ' % ) # * ( + 7 4 5 ! : < c 1 d ! 8 spi slave mode timing (ckeg=0) 1 7 1 k # a 1 / " k ( 8 / $ a / $ k # / $ k # a / $ k ( 7 / 9 < : < < b ! 5 8 1 7 1 k ( a 1 / " k ( 8 1 7 1 k # a 1 / " k # 8 1 7 1 k ( a 1 / " k # 8 7 1 / " k ( 8 7 1 / " k # 8 > : + ( * # ) % ' & & ' % ) # * ( + + ( * # ) % ' & & ' % ) # * ( + spi master mode timing 1 7 1 k # 8 1 7 1 k ( 8 > : + ( * # ) % ' & & ' % ) # * ( + 7 4 5 ! e ! 4 4 : p k c < ! c k # 8 $ @ < d a c / $ k # d / $ k ( a < e < d d ! 5 < < 6 spi slave mode timing (ckeg=1) ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 72 march 11, 2010 / $ k # k # q < ? 4 > < d q 7 k # q 8 $ ? d c < c 5 d q $ ? / $ < < c 4 c ! : / $ d 2 % @ ( 3 k ( ( ( a ( ( # a ( # ( a ( # # # ( ( 2 % @ ( 3 k # ( # $ spi transfer control flowchart ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 73 march 11, 2010 there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. a configuration option exists to allow a clock other than the system clock to drive the i 2 c interface. another configuration option determines the debounce time of the i 2 c inter - face. this uses the internal clock to in effect add a debounce time to the external clock to reduce the pos- sibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. sim function sim function sim interface or seg pins i 2 c clock i 2 c runs without internal clock disable/enable i 2 c debounce no debounce, 1 system clock; 2 system clocks i 2 c interface configuration options i 2 c registers there are three control registers associated with the i 2 c bus, simctl0, simctl1 and simar and one data register, simdr . the simdr register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simdr register. after the data is received from the i 2 c bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the i 2 c bus must be made via the simdr register. note that the simar register also has the name simctl2 which is used by the spi function. bits simidle , simen and bits sim0~sim2 in register simctl0 are used by the i 2 c interface. the simctl0 register is shown in the above spi section. simidle the simidle bit is used to select if the i 2 c interface continues running when the device is in the idle mode. setting the bit high allows the i 2 c interface to maintain operation when the device is in the idle mode. clearing the bit to zero disables any i 2 cop - erations when in the idle mode. this spi/i 2 c idle mode control bit is located at clkmod register bit4. simen the simen bit is the overall on/off control for the i 2 c interface. when the simen bit is cleared to zero to disable the i 2 c interface, the sda and scl lines will be in a floating condition and the i 2 c operating cur- rent will be reduced to a minimum value. in this con- dition the pins can be used as seg functions. when the bit is high the i 2 c interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the i 2 c control registers will be in an unknown condition and should therefore be first initialised by the application program. sim0~sim2 these bits setup the overall operating mode of the sim function. to select the i 2 c function, bits sim2~ sim0 should be set to the value 110. ! < c d < d d d c 4 = e < d ! c < d d c 4 = e < d ! c < ! < c % ! 7 8 < d d ! 7 8 5 c ! 4 < . d d 4 5 b % : > : 4 < > < 4 > : d d > / < < 4 = e < d ! d e < b b . b i 2 c block diagram ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 74 march 11, 2010 rxak the rxak flag is the receive acknowledge flag. when the rxak bit has been reset to zero it means that a correct acknowledge signal has been re - ceived at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxak bit to determine if the receiver wishes to receive the next byte. the trans - mitter will therefore continue sending out data until the rxak bit is set high. when this occurs, the transmitter will release the sda line to allow the master to send a stop signal to release the bus. srw the srw bit is the slave read/write bit. this bit de - termines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address match, that is when the haas bit is set high, the device will check the srw bit to determine whether it should be in transmit mode or receive mode. if the srw bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. when the srw bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. txak the txak flag is the transmit acknowledge flag. af - ter the receipt of 8-bits of data, this bit will be trans - mitted to the bus on the 9th clock. to continue receiving more data, this bit has to be reset to zero before further data is received. htx the htx flag is the transmit/receive mode bit. this flag should be set high to set the transmit mode and low for the receive mode. hbb the hbb flag is the i 2 c busy flag. this flag will be high when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be reset to zero when the bus is free which will occur when a stop signal is detected. hass the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the ad - dresses match then this bit will be high, if there is no match then the flag will be low. hcf the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon com - pletion of an 8-bit data transfer the flag will go high and an interrupt will be generated. i 2 c control register simar the simar register is also used by the spi interface but has the name simctl2. the simar register is the location where the 7-bit slave address of the microcontroller is stored. bits 1~7 of the simar register define the microcontroller slave ad - dress. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simar register, the microcontroller slave device will be selected. note that the simar register is the same register as simctl2 which is used by the spi interface. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address trans - mission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all de - vices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haas bit in the simctl1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service rou - tine, the microcontroller slave device must first check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the microcontroller to de- termine whether to go into transmit or receive mode. be- fore any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simar. step 2 set the simen bit in the simctl0 register to 1 to en - able the i 2 c bus. step 3 set the esim bit of the interrupt control register to en - able the i 2 c bus interrupt. $ % " ) ( % + $ > < d a d g ( g % d 4 < d d ( ) ' * ( & % # i 2 c slave address register simar ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 75 march 11, 2010 start signal the start signal can only be generated by the mas - ter device connected to the i 2 c bus and not by the microcontroller , which is only a slave device. this start signal will be detected by all devices con - nected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to deter - mine which slave device the master wishes to com - municate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, de - fines the read/write status and will be saved to the srw bit of the simctl1 register. the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the in- terrupt source has come from a matching slave ad- dress or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simdr register, or in the receive mode where it must implement a dummy read from the simdr regis- ter to release the scl line. srw bit the srw bit in the simctl1 register defines whether the microcontroller slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. if the srw bit is set to 1 then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw bit is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the microcontroller slave device must be setup to read data from the i 2 c bus as a receiver. acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas bit is high, the addresses have matched and the microcontroller slave device must check the srw srw bit to determine if it is to be a transmitter or a re - ceiver. if the srw bit is high, the microcontroller slave device should be setup to be a transmitter so the htx bit in the simctl1 register should be set to 1 if the srw bit is low then the microcontroller slave device should be setup as a receiver and the htx bit in the simctl1 register should be set to 0 . data byte the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge sig- nal, level 0 , before it can receive the next data byte. if the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the sda line and the master will send out a stop signal to re- lease control of the i 2 c bus. the corresponding data will be stored in the simdr register. if setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the simdr regis - ter. if setup as a receiver, the microcontroller slave de - vice must read the transmitted data from the simdr register. receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the microcontroller slave device, which is setup as a transmitter will check the rxak bit in the simctl1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. < d d / 2 % @ ( 3 k # # ( / / $ % : : > k q / < < / / b c : > " ! / b < < b d 4 d e 5 ! % : " ! i 2 c bus initialisation flow chart < < < e 4 5 ! > data timing diagram ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 76 march 11, 2010 b k # q b . k # q k # q ? $ ? $ . 1 k # q ? $ $ d c / ? : d c / / / b . : d b . . 1 / / b . . 1 i 2 c bus isr flow chart # ( # ( ( # (( # ( ( # ( # ( # # k 7 # 8 k < d d 7 + 8 k 7 # 8 k < d 4 d 4 = e < d ! 7 # 8 k 7 8 k 1 7 . 1 c a . 1 c 4 # 8 k > 7 # 8 1 1 > < d d i 2 c communication timing diagram ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 77 march 11, 2010 spi interface the devices contain an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. the spi interface is a full duplex serial data link, origi - nally designed by motorola, which allows multiple de - vices connected to the same spi bus to communicate with each other. the devices communicate using a mas - ter/slave technique where only the single master device can initiate a data transfer. a simple four line signal bus is used for all communication. spi interface communication four lines are used for each function. these are, sdi1 serial data input, sdo1 serial data output, sck1 se - rial clock and scs1 slave select. note that the condi - tion of the slave select line is conditioned by the csen1 bit in the spictl1 control register. if the csen1 bit is high then the scs1 line is active while if the bit is low then the scs line will be in a floating condition. the ac - companying timing diagram depicts the basic timing protocol of the spi bus. spi registers there are three registers for control of the spi interface. these are the two control registers spictl0 and spictl1 and the sbdr data register. the spictl0 register is used for the overall spi enable/disable, mas - ter/slave selection and clock selection. the spictl1 register is used for spi setup including, clock polarity, edge selection as well as certain status flags. the sbdr register is used for data storage. after power on, the contents of the sbdr register will be in an unknown condition. note that data written to the sbdr register will only be written to the txrx buffer, whereas data read from the sbdr register will actual be read from the register. spidr register bit76543210 name spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w porxxxxxxxx x unknown bit 7 spd7~spd0 : spi data spictl0 register bit76543210 name sp12 sp11 sp10 spien r/w r/w r/w r/w por11100000 bit 7~5 spi2~spi0 : master/slave clock select 000: spi master, f sys /4 001: spi master, f sys /16 010: spi master, f sys /64 011: spi master, f sub 100: spi master, timer 0 output/2 (pfd0) 101: spi slave bit 4~2 unimplemented, read as 0 bit 1 spien : spi enable/disable 0: disable 1: enable bit 0 unimplemented, read as 0 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 78 march 11, 2010 spictl1 register bit76543210 name ckpol1 ckeg1 mls1 csen1 wcol1 trf1 r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 unimplemented, read as 0 bit 5 ckpol1 : determines the base condition of the clock line 0: sck1 line high when the clock is inactive 1: sck1 line low when the clock is inactive the ckpol1 bit determines the base condition of the clock line, if the bit is high, then the sck1 line will be low when the clock is inactive. when the ckpol1 bit is low, then the sck1 line will be high when the clock is inactive. bit 4 ckeg1 : determines the spi1 sck1 active clock edge type ckpol1=0: 0: sck1 has high base level with data capture on sck1 rising edge 1: sck1 has high base level with data capture on sck1 falling edge ckpol1=1: 0: sck1 has low base level with data capture on sck1 falling edge 1: sck1 has low base level with data capture on sck1 rising edge the ckeg1 and ckpol1 bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. the ckpol1 bit determines the base condition of the clock line, if the bit is high, then the sck1 line will be low when the clock is inactive. when the ckpol1 bit is low, then the sck1 line will be high when the clock is inactive. the ckeg1 bit determines active clock edge type which depends upon the condition of ckpol1 bit. bit 3 mls1 : determines the data shift order - msb or lsb 0: lsb transmitted first 1: msb transmitted first bit 2 csen1 : spi1 bus select 0: disable - spi1 bus is floating 1: enable bit 1 wcol1 : write collision flag 0: collision free 1: collision detected this flag is set by the by the spi1 bus and cleared by the application program. the flag will be set to 1 if data is written to the spidr register (txrx buffer) when a data is still being transferred. any such data write actions will be ignored in such cases. bit 0 trf1 : transmit/receive completion flag 0: not complete 1: data transmission/reception complete this flag will be set high when a data reception or transmission has completed. it must be cleared using the application program and can be used to generate an interrupt. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 79 march 11, 2010 spi bus enable/disable to enable the spi bus, the sben bit should be set high, then wait for data to be written to the sbdr (txrx buffer) register. for the master mode, after data has been written to the sbdr (txrx buffer) register then transmission or reception will start automatically. when all the data has been transferred, the trf1 bit should be set. for the slave mode, when clock pulses are re - ceived on sck1, data in the txrx buffer will be shifted out or data on sdi1 will be shifted in. when the spi bus is disabled, sck1, sdi1, sdo1 and scs1 will be setup as i/o pins. spi operation the spi is selected using the application program. all communication is carried out using the 4-line interface for both master or slave mode. the csen1 bit in the spictl1 register controls the scsb line of the spi in - terface. setting this bit high, will enable the spi interface by allowing the scs1 line to be active, which can then be used to control the spi interface. if the csen1 bit is low, the scs1 line will be in a floating condition and can therefore not be used for control of the spi interface. when the csen1 bit is set high then sdi1 line will be placed in a floating condition and the sdo1 line will be high. if in the master mode, the sck1 line will be either high or low depending upon the clock polarity configura- tion option. if in the slave mode the sck1 line will be in a floating condition. if csen1 is low then the bus will be disabled and scs1, sdi1, sdo1 and sck1 will all be in a floating condition. the spi function keeps running in the idle mode - the spi module can still operate after a halt instruction is executed. the ckeg1 and ckpol1 bits must be setup before the spi is enabled; otherwise undesired clock edge may be generated. in the master mode, the master will always generate the clock signal. the clock and data transmission will be ini - tiated after data has been written to the sbdr register. in the slave mode, the clock signal will be received from an external master device for both data transmission or reception. the following sequences show the order to be followed for data transfer in both master and slave modes: master mode step 1 setup the spi2~spi0 bits in the spictl0 control register to select the master mode and the required clock speed. values of 000~101 can be selected. step 2 setup the spien bit and setup the mls1 bit to choose if the data is msb or lsb first, this must be same as the slave device. step 3 setup the csen1 bit in the spictl1 control regis - ter to enable the spi interface. step 4 for write operations: write the data to the sbdr register, which will actually place the data into the txrx buffer. then use the sck1 and scs1 lines to output the data. then goto to step 5. for read oper - ations: the data transferred in on the sdi1 line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 5 check the wcol1 bit, if set high then a collision er - ror has occurred so return to step 4. if zero then go to the following step. step 6 check the trf1 bit or wait for an spi serial bus in - terrupt. step 7 read data from the sbdr register. step 8 clear flag trf1. step 9 goto step 4. slave mode step 1 setup the spi2~spi0 bits to 101 to select the slave mode. step 2 setup the spien bit and setup the mls1 bit to choose if the data is msb or lsb first, this must be same as the master device. step 3 setup the csen1 bit in the spictl1 control regis- ter to enable the spi interface. step 4 for write operations: write data to the sbdr regis- ter, which will actually place the data into the txrx register, then wait for the master clock and scs1 signal. after this goto step 5. for read operations: the data transferred in on the sdi1 line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 5 check the wcol1 bit, if set high then a collision er - ror has occurred so return to step 4. if equal to zero then goto the following step. step 6 check the trf1 bit or wait for an spi interrupt. step 7 read data from the sbdr register. step 8 clear trf1 step 9 goto step 4 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 80 march 11, 2010 spi configuration options a configuration option is provided for an overall on/off control for the spi bus. additional configuration options are provided to enable operation of the wcol1 bit which is the write collision bit and the csen1 bus select bit. peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with an i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can origi - nate from either the timer/event counter 0 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to 1 enables the peripheral clock, setting pcken bit to 0 disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock out - put. simc0 register bit76543210 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por1110000 bit 7~5 sim2, sim1, sim0 : sim operating mode control described in sim section bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control described in sim section bit 0 unimplemented, read as 0 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 81 march 11, 2010 buzzer operating in a similar way to the programmable fre - quency divider, the buzzer function provides a means of producing a variable frequency output, suitable for applications such as piezo-buzzer driving or other ex - ternal circuits that require a precise frequency genera - tor. the bz and bz pins form a complementary pair, and are pin-shared with i/o pins, pb4 and pb5. a configura - tion option is used to select from one of three buzzer op - tions. the first option is for both pins pb4 and pb5 to be used as normal i/os, the second option is for both pins to be configured as bz and bz buzzer pins, the third op - tion selects only the pb4 pin to be used as a bz buzzer pin with the pb5 pin retaining its normal i/o pin function. note that the bz pin is the inverse of the bz pin which to - gether generate a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the internal clock source, , which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from f s /2 2 to f s /2 9 . the clock source that generates f s , which in turn controls the buzzer fre - quency, can originate from three different sources, the 32768hz oscillator, the 32k_int oscillator or the sys - tem oscillator/4, the choice of which is determined by the f s clock source configuration option. note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock f s and the internal division ratio. there are no internal registers associated with the buzzer frequency. if the configuration options have selected both pins pb4 and pb5 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by set - ting bits pbc4 and pbc5 of the pbc port control regis - ter to zero. the pb4 data bit in the pb data register must also be set high to enable the buzzer outputs, if set low, both pins pb4 and pb5 will remain low. in this way the single bit pb4 of the pb register can be used as an on/off control for both the bz and bz buzzer pin outputs. note that the pb5 data bit in the pb register has no con - trol over the bz buzzer pin pb5. c : 4 c ! : > c ? ' & % + * b i & % 1 r $ c ! : > d % % f % , c 0 0 buzzer function pb4/pb5 pin function control pbc register pbc4 pbc register pbc5 pb data register pb4 pb data register pb5 output function 001x pb4=bz pb5=bz 000x pb4= 0 pb5= 0 011x pb4=bz pb5=input line 010x pb4= 0 pb5=input line 10xd pb4=input line pb5=d 11xx pb4=input line pb4=input line x stands for don t care d stands for data 0 or 1 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 82 march 11, 2010 if configuration options have selected that only the pb4 pin is to function as a bz buzzer pin, then the pb5 pin can be used as a normal i/o pin. for the pb4 pin to func - tion as a bz buzzer pin, pb4 must be setup as an output by setting bit pbc4 of the pbc port control register to zero. the pb4 data bit in the pb data register must also be set high to enable the buzzer output, if set low pin pb4 will remain low. in this way the pb4 bit can be used as an on/off control for the bz buzzer pin pb4. if the pbc4 bit of the pbc port control register is set high, then pin pb4 can still be used as an input even though the configuration option has configured it as a bz buzzer output. note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the con - figuration option selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the ac - tual function of the pin can be changed dynamically by the application program by programming the appropri - ate port control register bit. < < 4 = : 4 ' 0 : > : ' 0 : > : ) ) buzzer output pin control note: the above drawing shows the situation where both pins pb4 and pb5 are selected by configuration option to be bz and bz buzzer pin outputs. the port control register of both pins must have already been setup as out- put. the data setup on pin pb5 has no effect on the buzzer outputs. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 83 march 11, 2010 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or time base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main pro - gram allowing the microcontroller to direct attention to their respective needs. the devices contain a single external interrupt and mul - tiple internal interrupts. interrupt register overall interrupt control, which means interrupt en - abling and request flag setting, is controlled by using several registers, intc0, intc1, mfic0 and mfic1. by controlling the appropriate enable bits in this registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding re - quest flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a range of internal and external events can all generate an interrupt, by setting their correspponding request flag, if their appropriate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt ser - vice routine. here is located the code to control the ap - propriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and al - lows the microcontroller to continue with normal execu - tion at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the following dia - gram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt re - quests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. when an interrupt request is generated it takes 2 or 3 in - struction cycle before the program jumps to the interrupt vector. if the device is in the sleep or idle mode and is woken up by an interrupt request then it will take 3 cy - cles before the program jumps to the interrupt vector. wait for 2 ~ 3 instruction cycles main program isr entry enable bit set ? main program reti (it will set emi automatically) automatically disable interrupt clear emi & request flag interrupt request or interrupt flag set by instruction y n interrupt flow ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 84 march 11, 2010 : 4 < < < d 9 4 > c a a d % : < < < d c e : 4 < < < d / < d : < < b ! 5 : > < < ! / 9 < : > h : < ! / # / / ( / : ( : > h : < ! ( / / # / ( / : # : > h : < ! # / # % : > h : < ! / / 9 < : > h : < ! / ( : < c : 4 : > h : < ! / / e : > h : < ! / < < 4 = : > h : < ! / : > h : < ! / / / 9 < > 5 < : > h : < ! / / : % : > h : < ! % / % / : & : > h : < ! & / & : > h : < ! / interrupt structure ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 85 march 11, 2010 interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. ht56r22 interrupt source priority vector external interrupt 0 1 04h external interrupt 1 2 08h timer/event counter 0 overflow 3 0ch timer/event counter 1 overflow 4 10h spi/i 2 c interrupt 5 14h time base interrupt 6 18h rtc interrupt 6 18h a/d converter interrupt 6 18h external peripheral interrupt 6 18h spi interrupt 6 18h ht56r23/ht56r24 interrupt source priority vector external interrupt 0 1 04h external interrupt 1 2 08h timer/event counter 0 overflow 3 0ch timer/event counter 1 overflow 4 10h spi/i 2 c interrupt 5 14h time base interrupt 6 18h rtc interrupt 6 18h a/d converter interrupt 6 18h external peripheral interrupt 6 18h spi1 6 18h timer/event counter 2 overflow 6 18h ht56r25/HT56R26 interrupt source priority vector external interrupt 0 1 04h external interrupt 1 2 08h timer/event counter 0 overflow 3 0ch timer/event counter 1 overflow 4 10h spi/i 2 c interrupt 5 14h time base interrupt 6 18h rtc interrupt 6 18h ht56r25/HT56R26 a/d converter interrupt 6 18h external peripheral interrupt 6 18h spi1 6 18h timer/event counter 2 overflow 6 18h timer/event counter 3 overflow 6 18h in cases where both external and internal interrupts are enabled and where an external and internal interrupt oc - curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. interrupt operation when the conditions for an interrupt event occur, such as a timer/event counter overflow, or a/d conversion completion etc, the relevant interrupt request flag will be set. whether the request flag actually generates a pro - gram jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the inter - rupt request flag is set an actual interrupt will not be gen - erated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be ex- ecuted, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service rou - tine. here is located the code to control the appropriate interrupt. the interrupt service routine must be termi - nated with a reti, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their or - der of priority. some interrupt sources have their own in - dividual vector while others share the same multi-function interrupt vector. once an interrupt sub - routine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further inter - rupt nesting from occurring. however, if other interrupt requests occur during this interval, although the inter - rupt will not be immediately serviced, the request flag will still be recorded. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 86 march 11, 2010 if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to al - low interrupt nesting. if the stack is full, the interrupt re - quest will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. in case of simulta - neous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request flags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occur - ring the corresponding flag should be set before the de - vice is in sleep or idle mode. external interrupt for an external interrupt to occur, the global interrupt en - able bit, emi, and external interrupt enable bits, eei0 and eei1, must first be set. additionally the correct inter - rupt edge type must be selected using the intedge register to enable the external interrupt function and to choose the trigger edge type. an actual external inter - rupt will take place when the external interrupt request flag, eif0 or eif1, is set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on the int0 or int1 pin. the external interrupt pins are pin-shared with the i/o pins pa4 and pa6 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the intc0 register has been set. the pin must also be setup as an input by setting the corresponding pac.4 and pac.6 bits in the port control register. when the interrupt is en - abled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h or 08h, will take place. when the interrupt is serviced, the external interrupt request flags, eif0 or eif1, will be automati - cally reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resis - tor selections on this pin will remain valid even if the pin is used as an external interrupt input. the intedge register is used to select the type of active edge that will trigger the external interrupt. a choice of ei - ther rising and falling edge types can be chosen along with an option to allow both edge types to trigger an ex - ternal interrupt. note that the intedge register can also be used to disable the external interrupt function. intedge register - all devices bit76543210 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 87 march 11, 2010 intc0 register - all devices bit76543210 name t0f int1f int0f t0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 t0f : timer/event counter 0 interrupt request flag 0: inactive 1: active bit 5 int1f : external interrupt 1 request flag 0: inactive 1: active bit 4 int0f : external interrupt 0 request flag 0: inactive 1: active bit 3 t0e : timer/event counter 0 interrupt enable 0: disable 1: enable bit 2 int1e : external interrupt 1 enable 0: disable 1: enable bit 1 int0e : external interrupt 0 enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable intc1 register - all devices bit76543210 name mff simf t1f mfe sime t1e r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 mff : multi-function interrupt request flag 1: active 0: inactive bit 5 simf : spi/i 2 c interrupt request flag 1: active 0: inactive bit 4 t1f : timer/event counter 1 interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 mfe : multi-function interrupt enable 0: disable 1: enable bit 1 sime : serial interface module interrupt enable 0: disable 1: enable bit 0 t1e : timer/event counter 1 interrupt enable 0: disable 1: enable ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 88 march 11, 2010 mfic0 register - all devices bit76543210 name xpf tbf rtf adf xpe tbe rte ade r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 xpf : external peripheral interrupt request flag 0: inactive 1: active bit 6 tbf : time base interrupt request flag 0: inactive 1: active bit 5 rtf : real time clock interrupt request flag 0: inactive 1: active bit 4 adf : a/d converter interrupt request flag 0: inactive 1: active bit 3 xpe : external peripheral interrupt enable 0: enable 1: disable bit 2 tbe : time base interrupt enable 0: enable 1: disable bit 1 rte : real time clock interrupt control 0: enable 1: disable bit 0 ade : a/d converter interrupt control 0: enable 1: disable mfic1 register - ht56r22 bit76543210 name spif spie r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as 0 bit 4 spif : spi interface interrupt request flag 0: inactive 1: active bit 3~1 unimplemented, read as 0 bit 0 spie : spi interface interrupt control 0: enable 1: disable ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 89 march 11, 2010 mfic1 register - ht56r23/ht56r24 bit76543210 name t2f spif spie r/w r/w r/w r/w por 00 00 bit 7~6 unimplemented, read as 0 bit 5 t2f : timer/event counter 2 interrupt request flag 0: inactive 1: active bit 4 spif : spi interface interrupt request flag 0: inactive 1: active bit 3~2 unimplemented, read as 0 bit 1 t2e : timer/event counter 2 interrupt control 0: enable 1: disable bit 0 spie : spi interface interrupt control 0: enable 1: disable mfic1 register - ht56r25/HT56R26 bit76543210 name t3f t2f sspifpif t3e t2e spie r/w r/w r/w r/w por 00 0 bit 7 unimplemented, read as 0 bit 6 t3f : timer/event counter 2 interrupt request flag 0: inactive 1: active bit 5 t2f : timer/event counter 2 interrupt request flag 0: inactive 1: active bit 4 spif : spi interface interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 t3e : timer/event counter 2 interrupt control 0: enable 1: disable bit 1 t2e : timer/event counter 2 interrupt control 0: enable 1: disable bit 0 spie : spi interface interrupt control 0: enable 1: disable ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 90 march 11, 2010 timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, tne, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, tnf, is set, a situation that will occur when the relevant timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer in - terrupt request flag, tnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. time base interrupt for a time base interrupt to occur the global interrupt en - able bit emi and the corresponding interrupt enable bit tbe, must first be set. an actual time base interrupt will take place when the time base request flag tbf is set, a situation that will occur when the time base overflows. when the interrupt is enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will take place. when the interrupt is serviced, the time base interrupt flag. tbf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. a/d converter interrupt the a/d converter interrupt is controlled by the termina- tion of an a/d conversion process. an a/d converter in- terrupt request will take place when the a/d converter interrupt request flag, adf, is set, which occurs when the a/d conversion process finishes. to allow the pro- gram to branch to its respective interrupt vector ad - dress, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, and multi-function interrupt enable bits, must first be set.must first be set. when the interrupt is enabled, the stack is not full and the a/d con - version process has ended, a subroutine call to the multi-function interrupt vector, will take place. when the interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automat - ically cleared. as the adf flag will not be automatically cleared, it has to be cleared by the application program. serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function in - terrupt. a sim interrupt request will take place when the sim interrupt request flag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and multi-function interrupt enable bits, must first be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or re - ceived by the sim interface, a subroutine call to the multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, how - ever only the multi-function interrupt request flag will be also automatically cleared. as the simf flag will not be automatically cleared, it has to be cleared by the appli - cation program. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt re quest flag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector ad- dress, the global interrupt enable bit, emi, external pe- ripheral interrupt enable bit, xpe, and multi-function interrupt enable bit, must first be set. when the inter- rupt is enabled, the stack is not full and a negative tran- sition appears on the external peripheral interrupt pin, a subroutine call to the multi-function interrupt, will take place. when the external peripheral interrupt is serviced, the emi bit will be automatically cleared to dis - able other interrupts, however only the multi-function in - terrupt request flag will be also automatically cleared. as the xpf flag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be prop - erly configured to enable it to operate as an external pe - ripheral interrupt pin. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 91 march 11, 2010 multi-function interrupt within these devices there is a multi-function interrupt. unlike the other independent interrupts, these inter - rupts have no independent source, but rather are formed from other existing interrupt sources. a multi-function interrupt request will take place when the multi-function interrupt request flag, mff is set. the multi-function interrupt flag will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective in - terrupt vector address, when the multi-function inter - rupt is enabled and the stack is not full, and either one of the interrupts contained the multi-function interrupt oc - curs, a subroutine call to the multi-function interrupt vec - tor will take place. when the interrupt is serviced, the multi-function request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt flag will be automatically reset when the interrupt is serviced, the request flag from the original source of the multi-function interrupt, will not be automatically reset and must be manually reset by the application program. programming considerations by disabling the interrupt enable bits, a requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the idle/sleep mode. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. lcd scom function the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~ scom3, are pin shared with certain pin on the pb0~ pb3 port. the lcd signals (com and seg) are gener - ated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pb0~pb3 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this en - ables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1 / 2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port b pins are used for lcd driving. note that the port control register does not need to first setup the pins as outputs to enable the lcd driver operation. scomen comnen pin function o/p level 0 x i/o 0or1 1 0 i/o 0or1 1 1 scomn v dd /2 output control - ( f & / $ / $ - % > ! 4 : lcd com bias ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 92 march 11, 2010 lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is be - ing used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register b i t76543210 name isel scomen com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7, 6 unimplemented, read as 0 bit 5 isel : scom operating current selection (v dd =5v) 0: 25 a 1: 50 a bit 4 scomen : scom module on/off control 0: disable 1: enable scomn can be enable by comnen if scomen=1 bit 3 com3en : pb3 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pb2 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pb1 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pb0 or scom0 selection 0: gpio 1: scom0 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 93 march 11, 2010 digital to analog converter dac all devices include a 12-bit digital to analog converter function. this function allows digital data contained in the device to generate audio signals. operation the data to be converted is stored in two registers dal and dah. the dah register stores the highest 8-bits, da4~da11, while dal stores the lowest 4-bits, da0~da3. an additional control register, dactrl, pro - vides overall dac on/off control in addition to a 3-bit 8-level volume control. the dac output is channeled to pin aud which is pin-shared with i/o pin pb5. when the dac is enabled by setting the dacen pin high, then the original i/o function will be disabled, along with any pull-high resistor options. dach register b i t76543210 name da11 da10 da9 da8 da7 da6 da5 da4 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 00000000 bits 7~0 da11~da0: audio output dac high byte bits dacl register b i t76543210 name da3 da2 da1 da0 r/w r/w r/w r/w r/w por 00000000 bits 7~4 da3~da0: audio output dac low bits bits 3~0 unimplemented, read as 0 dactl register b i t76543210 name vol2 vol1 vol0 dacen r/w r/w r/w r/w r/w por 00000000 bits 7~5 vol2~vol0 : audio volume control bits 4~1 unimplemented, read as 0 bit 0 dacen : dac on/off control 0: off 1: on the dac output is channeled to pin aud which is pin-shared with i/o pin pb5. when the dac is enabled by setting the dacen pin high, then the original i/o function will be disabled, along with any pull-high resistor options. the dac out - put reference voltage is the power supply voltage vdd. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 94 march 11, 2010 configuration options configuration options refer to certain options within the mcu that are programmed into the otp program memory de - vice during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defined for proper system function, the details of which are shown in the table. no. options oscillator options 1 high oscillator type selection - f m 1. external crystal oscillator 2. external rc oscillator 3. externally supplied clock - internal filter on 4. externally supplied clock - internal filter off 2 f sub clock selection: 1. 32768hz external oscillator 2. 32k_int internal oscillator 3f s clock selection: f sub or f sys /4 4 xtal mode selection: 455khz or 1m~12mhz 5 32768hz crystal: enable or disable pfd options 6 pa3: normal i/o or pfd output 7 pfd clock selection: timer/event counter 0 or timer/event counter 1 buzzer options 8 pa0/pa1: normal i/o or bz/bz or pa0=bz and pa1 as normal i/o 9 buzzer frequency: f s /2 2 ,f s /2 3 ,f s /2 4 ,f s /2 5 ,f s /2 6 ,f s /2 7 ,f s /2 8 ,f s /2 9 time base option 10 time base time-out period: 2 12 /f s ,2 13 /f s ,2 14 /f s ,2 15 /f s , lcd option 11 lcd type: r or c - ht56r66 only watchdog options 12 watchdog timer function: enable or disable 13 clrwdt instructions: 1 or 2 instructions 14 wdt time-out period: 2 12 /f s ~2 13 /f s ,2 13 /f s ~2 14 /f s ,2 14 /f s ~2 15 /f s ,2 15 /f s ~2 16 /f s lvd/lvr options 15 lvd function: enable or disable 16 lvr function: enable or disable 17 lvr/lvd voltage: 2.1v/2.2v or 3.15v/3.3v or 4.2v/4.4v spi options 18 sim pin enable/disable 19 spi_wcol: enable/disable 20 spi_csen: enable/disable, used to enable/disable (1/0) software csen function i 2 c option 21 i 2 c debounce time: no debounce, 1 system clock debounce, 2 system clock debounce application circuits ht56r22 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 95 march 11, 2010 no. options pintb option 22 external peripheral interrupt or segment function timer/event counter and external interrupt pins filter option 23 interrupt and timer/event counter input pins internal filter on/off control applies to all pins lock options 24 lock all 25 partial lock # % 4 : % % ) * # ( ! % * ( ! ' ( $ ( # $ # % ( $ % & $ & ' $ ( $ ' ) ( # $ ) * $ # # $ * + # 1 # $ + ( 1 ( # # % 1 % & $ & ' 0 ) 0 ( f & ( ( # # % % # . # . % 4 : % % ) * # ( ! % * ( ! ' / + - - ( 6 # - % ) % ( + * , ( ( 6 # f # # ( = f # ( ( = & ( ( ( 6 ( # # $ ' # ' ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 96 march 11, 2010 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 97 march 11, 2010 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 98 march 11, 2010 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 99 march 11, 2010 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 100 march 11, 2010 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 101 march 11, 2010 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 102 march 11, 2010 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 103 march 11, 2010 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 104 march 11, 2010 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 105 march 11, 2010 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 106 march 11, 2010 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 107 march 11, 2010 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 108 march 11, 2010 package information 16-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 780 880 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ms-001d (see fig2) symbol dimensions in mil min. nom. max. a 735 775 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 109 march 11, 2010 # * # , / " b fig1. full lead packages # * # , / " b fig2. 1 / 2 lead packages mo-095a (see fig2) symbol dimensions in mil min. nom. max. a 745 785 b 275 295 c 120 150 d 110 150 e14 22 f45 60 g 100 h 300 325 i 430 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 110 march 11, 2010 16-pin nsop (150mil) outline dimensions symbol dimensions in mil min. nom. max. a 228 244 b 149 157 c1 4 20 c 386 394 d5 3 69 e 50 f4 10 g2 2 28 h4 12 0 10 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 111 march 11, 2010 # * # , / " b o 16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.189 0.197 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 4.80 5.00 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 112 march 11, 2010 # * # , / o " b 20-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 980 1060 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 mo-095a (see fig2) symbol dimensions in mil min. nom. max. a 945 985 b 275 295 c 120 150 d 110 150 e14 22 f45 60 g 100 h 300 325 i 430 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 113 march 11, 2010 % ( # # # # ( / " b fig1. full lead packages % ( # # # # ( / " b fig2. 1 / 2 lead packages 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 496 512 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 114 march 11, 2010 % ( # # # # ( / o " b 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.158 c 0.008 0.012 c 0.335 0.347 d 0.049 0.065 e 0.025 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 4.01 c 0.20 0.30 c 8.51 8.81 d 1.24 1.65 e 0.64 f 0.10 0.25 g 0.38 1.27 h 0.18 0.25 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 115 march 11, 2010 % ( # # # # ( / o " b 24-pin skdip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 1230 1280 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ms-001d (see fig2) symbol dimensions in mil min. nom. max. a 1160 1195 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 116 march 11, 2010 % ' # # & # % / " b fig1. full lead packages % ' # # & # % / " b fig2. 1 / 2 lead packages mo-095a (see fig2) symbol dimensions in mil min. nom. max. a 1145 1185 b 275 295 c 120 150 d 110 150 e14 22 f45 60 g 100 h 300 325 i 430 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 117 march 11, 2010 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 598 613 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 118 march 11, 2010 % ' # # & # % / o " b 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 119 march 11, 2010 % ' # # & # % / o " b 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 375 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 120 march 11, 2010 % # # ) # ' / " b 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 697 713 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 121 march 11, 2010 % # # ) # ' o " b / 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 122 march 11, 2010 % # # ) # ' o " b / 28-pin ssop (209mil) outline dimensions mo-150 symbol dimensions in mm min. nom. max. a 7.40 8.20 b 5.00 5.60 c 0.22 0.33 c 9.90 10.50 d 2.00 e 0.65 f 0.05 g 0.55 0.95 h 0.09 0.21 0 8 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 123 march 11, 2010 % # # ) # ' o " b / 44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in mm min. nom. max. a 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10 0 7 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 124 march 11, 2010 & ' # # # ' ' % % # % / " b s 1 & & % & 52-pin qfp (14mm 14mm) outline dimensions symbol dimensions in mm min. nom. max. a 17.30 17.50 b 13.90 14.10 c 17.30 17.50 d 13.90 14.10 e 1.00 f 0.40 g 2.50 3.10 h 3.40 i 0.10 j 0.73 1.03 k 0.10 0.20 0 7 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 125 march 11, 2010 & , ' ( ) % # % + # & # ' % * / " b s 1 product tape and reel specifications reel dimensions sop 16n (150mil), ssop 20s (150mil), ssop 24s (150mil), ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 ssop 16s symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.20.2 sop 20w, sop 24w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 126 march 11, 2010 # % ssop 28s (209mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 28.4 +0.3/-0.2 t2 reel thickness 31.1 (max.) carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 127 march 11, 2010 # # ( / 1 ( ( ( > 4 = ! > # d 5 < 5 < < 4 d 5 d 6 < b < sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 ssop 16s symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 5.50.1 d perforation diameter 1.550.10 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.40.1 b0 cavity width 5.20.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 9.30.1 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 128 march 11, 2010 ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.00.1 k0 cavity depth 2.30.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.50.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 129 march 11, 2010 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ssop 28s (209mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.2 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 8.40.1 b0 cavity width 10.650.10 k0 cavity depth 2.40.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 130 march 11, 2010 ht56r22/ht56r23/ht56r24/ht56r25/HT56R26 rev. 1.00 131 march 11, 2010 copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
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